Abstract
A processor in a multicomputer operates in an environment very different from that of a sequential computer. In addition to dealing with memory latency as in a sequential computer, a multicomputer processor must also communicate and synchronize with its peers. In such a system, a process may idle waiting for a memory reference, a message, or a synchronization event. By rapidly switching processes when waiting on an event, a multithreaded processor maximizes the utilization of the processor and its associated memory and network bandwidth in the presence of uncertain delays.
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Dally, W.J. (1994). Issues in the Design and Implementation of Instruction Processors for Multicomputers (Position Statement). In: Iannucci, R.A., Gao, G.R., Halstead, R.H., Smith, B. (eds) Multithreaded Computer Architecture: A Summary of the State of the ART. The Springer International Series in Engineering and Computer Science, vol 281. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-2698-8_3
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DOI: https://doi.org/10.1007/978-1-4615-2698-8_3
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