Multilayer MCM Routing

Abstract

The problem of routing the interchip connections in an MCM substrate differs from conventional on-chip routing in some fundamental ways. The very nature of the routing environment is different: in most VLSI design styles, such as the standard cell, sea-of-gates and macro-cell, the area available for routing intercell connections is divided into channels, and switchboxes as illustrated in Fig. 4.1. The routing process is thus naturally decomposed into two stages: global routing, in which routes for all nets are assigned to appropriate sequences of channels; and detailed routing, in which the wires in each channel and switch-box are ordered and assigned to specific layers such that design rule constraints are satisfied. Typically, there are only two or three layers available for signal wiring. These may differ significantly in their electrical properties, such as the resistance per square of the interconnect and the capacitance per unit area.