VLSI Implementation of a 100 Mhz Pipelined ADPCM Codec Chip

Abstract

In this chapter, we employ the pipelined ADPCM (PIPADPCM) codec studied in Chapter 3 and its finite-precision analysis studied in Chapter 6 to design an ADPCM video codec chip in 1.2j CMOS technology [Sha93e]. In the past, various schemes for intra-inter frame ADPCM coding schemes were investigated [Pir82]. Feasibility of a single chip DPCM codec was first indicated in [Pir85], where the critical path delay of the basic DPCM structure was reduced by one adder computation time. In [Bra87], a VLSI implementation of a DPCM coder in 2.5p CMOS with an off-chip quantizer had been presented. This coder was designed for a 10.7 MHz sampling rate. Another DPCM implementation in 2.0p CMOS for sampling rates of 15 MHz was presented in [Rot87]. A single-chip ADPCM coder, with an adaptive quantizer, was presented in [Sch89]. This implementation was in 1.5p CMOS technology and could operate at 26 MHz.