Skip to main content
SpringerLink
Log in

References

  • Chapter
Pipelined Adaptive Digital Filters

Part of the book series: The Springer International Series in Engineering and Computer Science ((SECS,volume 274))

  • 150 Accesses

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. M. R. Azimi-Sadjadi, T. Lu and E. M. Nebot, “Parallel and sequential block Kalman filtering and their implementations using systolic arrays”, IEEE Trans. on Signal Processing, vol. 39, no. 1, pp. 137–147, January 1991.

    Article  MATH  Google Scholar 

  2. U. Banerjee etal, “Time and parallel processor bounds for Fortran like loops”, IEEE Trans. on Computers, vol. 28, no.12, pp. 660–670, 1979.

    Article  MATH  Google Scholar 

  3. C. A. Belfiore and J. H. Park, Jr., “Decision feedback equalization”, Proc. IEEE, vol. 67, pp. 1143–1156, Aug. 1979.

    Article  Google Scholar 

  4. T. Berger, Rate Distortion Theory, Prentice-Hall Inc., Englewood Cliffs, NJ (1971).

    Google Scholar 

  5. R. C. Brainard and J. H. Othmer, “VLSI implementation of a DPCM compression algorithm for digital TV”, IEEE Trans. on Communications, vol. COM-35, no. 8, pp. 854–856, August 1987.

    Article  Google Scholar 

  6. C. Caraiscos and B. Liu, “A roundoff error analysis of the LMS adaptive algorithm”, IEEE Trans. Acoust. Speech, Signal Processing, vol. 32, pp. 34–41, Feb. 1984.

    MATH  Google Scholar 

  7. A. P. Chandrakasan, S. Sheng and R. W. Brodersen, “Low power CMOS digital design”, IEEE J. of Solid-State Circuits, vol. 27, pp. 473–484, April 1992.

    Article  Google Scholar 

  8. P.-C. Chang and R. M. Gray, “Gradient algorithms for designing predictive vector quantizers”, IEEE Trans. on Acoust., Speech and Signal Proc., vol. ASSP-34, no. 4, pp. 679–690, August 1986.

    Article  Google Scholar 

  9. J.-G. Chung and K. K. Parhi, “Pipelining of lattice IIR digital filters”, IEEE Trans. on Signal Processing,(to appear).

    Google Scholar 

  10. S. Chen and G. R. Arce, “Microstatistic LMS filtering”, IEEE Trans. on Signal Processing, vol. 41, no. 3, pp. 1021–1034, Jan. 1993.

    Article  MATH  Google Scholar 

  11. D. Chester, R. Young and M. Petrowski, “A fully systolic adaptive filter implementation”, Proc. 1990 Int. Conf. Acons., Speech,Signal Processing, Toronto, May 1991, pp. 2109–2112.

    Google Scholar 

  12. J.M. Cioffi, “The block-processing FTF adaptive algorithm”, IEEE Trans. on Acoustics,Speech and Signal Proc., vol. 34, pp. 77–90, Feb. 1986.

    Article  Google Scholar 

  13. J. M. Cioffi, P. Fortier, S. Kasturia, and G. Dudevoir, “Pipelining the decision feedback equalizer”, IEEE DSP Workshop, 1988.

    Google Scholar 

  14. J. M. Cioffi, W. L. Abbot, H. K. Thapar, C. M. Melas, and K. D. Fisher, “Adaptive equalization in magnetic-disk storage channels”, IEEE Communications Magazine, pp. 14–29, February 1990.

    Google Scholar 

  15. G.A. Clark, S.K. Mitra and S.R. Parker, “Block implementation of adaptive digital filters”IEEE Trans. on Acoustics,Speech and Signal Proc., vol. 29, pp. 744–752, June 1981.

    Article  MATH  Google Scholar 

  16. E. J. Coyle, J. Lin, and M. Gabbouj, “Optimal stack filtering, estimation and structural approaches to image processing”, IEEE Trans. on Acoustics, Speech and Sig. Proc., vol. 37, no. 12, Dec. 1989.

    Google Scholar 

  17. P. Cummiskey, et. al., “Adaptive quantization in differential PCM coding of speech”, Bell System Technical Journal, vol. 52, pp. 1105–1119, Sept. 1973.

    Google Scholar 

  18. V. Cuperman and A. Gersho, “Adaptive differential vector coding of speech”, Conference Record, GlobeCom 82, pp. 1092–1096, Dec. 1982.

    Google Scholar 

  19. G. W. Davidson, et al, “An investigation of block adaptive decision feedback equalization for frequency selective fading”, IEEE Int. Conf. on Communications, 1988.

    Google Scholar 

  20. P. Denyer, and D. Renshaw, VLSI Signal Processing: A Bit-Serial Approach, Reading, MA: Addison-Wesley, 1985.

    Google Scholar 

  21. M. Dunham and R. M. Gray, “An algorithm for the design of labelled transition finite-state vector quantizers”, IEEE Trans. Commun., vol. COMM-33, pp. 83–89, Jan. 1985.

    Article  Google Scholar 

  22. D. D. Falconer and L. Ljung, “Application of fast Kalman estimation to adaptive equalization”, IEEE Trans. on Communications, vol. COM-26, no. 10, pp. 1439–1446, October 1978.

    Article  Google Scholar 

  23. G. Fettweis and H. Meyr, “Parallel Viterbi decoding by breaking the compare-select feedback bottleneck”, IEEE Trans. on Communications, vol. 37, pp. 785–790, Aug. 1989.

    Article  Google Scholar 

  24. K. D. Fisher, J. M. Cioffi, W. L. Abbot, P. S. Bednarz, and C. M. Melas, “An adaptive RAM-DFE for storage channels”, IEEE Trans. on Communications, vol. 39, pp. 1559–1568, November 1991.

    Article  Google Scholar 

  25. G. F. Franklin, J. D. Powell, and M. L. Workman, Digital Control of Dynamical Systems, Addison-Wesley, 1990.

    Google Scholar 

  26. W. A. Gardner, “Learning characteristics of stochastic gradient descent algorithms: A general study, analysis and critique”, Signal Processing, vol. 6, pp. 113–133, 1984.

    Article  MathSciNet  Google Scholar 

  27. A. Gatherer and T. H.-Y. Meng, “High sampling rate adaptive decision feedback equalizer”, IEEE Trans. on Signal Processing, vol. 41, pp. 1000–1005, Feb. 1993.

    Article  Google Scholar 

  28. W. M. Gentleman and H. T. Kung, “Matrix triangularization by systolic arrays”, Proc. SPIE, vol. 298, Real-Time Signal Processing IV, pp. 298–303, 1983.

    Google Scholar 

  29. D. Godard, “Channel equalization using a Kalman filter for fast data transmission”, IBM J. Res. Develop., pp. 267–273, May 1974.

    Google Scholar 

  30. R. M. Gray, “Vector quantization”, IEEE ASSP Mag., pp. 4–29, Apr. 1984.

    Google Scholar 

  31. R. I. Hartley and P. F. Corbett, “Digit-serial processing techniques”, IEEE Trans. on Circuits and Systems, vol. 37, pp. 707–719, June 1990.

    Article  Google Scholar 

  32. ] M. Hatamian and G. L. Cash, “A 70-MHz, 8-bitx8-bit parallel pipelined multiplier in 2.5p CMOS”, IEEE J. of Solid-State Circuits, vol. 21, no. 4, August 1986.

    Article  Google Scholar 

  33. M. Hatamian and G. L. Cash, “Parallel bit-level pipelined VLSI designs for high-speed signal processing”, Proc. of IEEE, vol. 75, no. 9, Sept. 1987.

    Article  Google Scholar 

  34. M. Hatamian and K.K. Parhi, “An 85 MHz 4th order programmable IIR digital filter chip”, IEEE Journal of Solid-State Circuits, vol. 27, pp. 175–183, Feb. 1992.

    Article  Google Scholar 

  35. S. Haykin, Adaptive Filter Theory. New Jersey: Prentice-Hall, 1986.

    Google Scholar 

  36. S. M. Heemstra de Groot, S. H. Gerez, and O. E. Hermann, “Range chart guided iterative data-flow graph scheduling”, IEEE Trans. on Circuits and Systems-I: Fundamental Theory and Applications, vol. 39, no. 5, pp. 351–364, May 1992.

    Article  MATH  Google Scholar 

  37. J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantita- tive Approach, San Mateo, CA: Morgan Kaufman Publishers, 1989.

    Google Scholar 

  38. M.L. Honig and D.G. Messerschmitt, Adaptive Filters: Structures,Algorithms, and Applications. Boston: Kluwer, 1984.

    Google Scholar 

  39. K. Hwang and F. A. Briggs, Computer Architecture and Parallel Processing, New York: McGraw Hill, 1984.

    Google Scholar 

  40. C.-T. Hwang, J.-H. Lee, and Y.-C. Hsu, “A formal approach to the scheduling problem in high-level synthesis”, IEEE Trans. on CAD of IC’s, vol. 10, no. 4, pp. 464–475, April 1991.

    Google Scholar 

  41. R. Jain et al, “Custom design of a VLSI PCM-FDM transmultiplexor from system specifications to circuit layout using a computer-aided design system”, IEEE Trans. on Circuits and Systems, vol. 33, no. 2, pp. 73–85, Feb. 1986.

    Article  Google Scholar 

  42. N. S. Jayant, “Adaptive quantization with one-word memory”, Bell System Technical Journal, vol. 52, pp. 1119–1145, Sept. 1973.

    Google Scholar 

  43. D. L. Jones, “Learning characteristics of transpose-form LMS adaptive filters”, IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing, vol. 39, pp. 745–749, Oct. 1992.

    Article  MATH  Google Scholar 

  44. N. Jouppi and D. Wall, “Available instruction level parallelism for super-scalar and super-pipelined machines”, in Proc. of 3rd Int. Conf. on Architectural Support for Programming Languages and Operating Systems, Boston, May 1989, pp. 272–282.

    Google Scholar 

  45. T. Kailath, “Estimating filters for linear time-invariant channels”, MIT Research Lab. for Electronics, Quarterly Progress Report, No. 58, pp. 185–197,1960.

    Google Scholar 

  46. R. E. Kalman, “A new approach to linear and prediction problems”, J. Basic Eng., vol. 82, pp. 35–45, 1960.

    Article  Google Scholar 

  47. S. Kasturia, J. T. Aslanis, and J. M. Cioffi, “Vector coding for partial response channels”, IEEE Trans. Info. Theory, vol. 36, pp. 741–753, July 1990.

    Article  MathSciNet  Google Scholar 

  48. J. Kim and L.D. Davisson, “Adaptive linear estimation for stationary M-dependent processes”, IEEE Trans. Inform. Theory, vol. IT-21, pp. 23–31, Jan. 1975.

    Article  MathSciNet  Google Scholar 

  49. P.M. Kogge, “Parallel solution of recurrence problems”, IBM J. Res. Develop., vol. 18, pp. 138–148, March 1974.

    Article  MathSciNet  MATH  Google Scholar 

  50. P.M. Kogge, The Architecture of Pipelined’ Computers, New York: McGraw Hill, 1981.

    Google Scholar 

  51. K. Konstantinides and N. Kanopoulos, “Design alternatives for adaptive digital lattice filters and a new bit-serial architecture”, IEEE Trans. Circuits and Systems, vol. CAS-34, no. 7, July 1987.

    Google Scholar 

  52. H. T. Kung, “Why systolic arrays ?”, IEEE Computer, pp. 37–46, January 1982.

    Google Scholar 

  53. S-Y. Kung, “On supercomputing with systolic/wavefront array proces-sors”, Proceedings of the IEEE, vol. 72, pp. 867–884, July 1984.

    Article  Google Scholar 

  54. S.-Y. Kung and J.-N. Hwang, “Systolic array designs for Kalman filtering”, IEEE Trans. on Signal Processing, vol. 39, no. 1, pp. 171–182, January 1991.

    Article  MATH  Google Scholar 

  55. M. Lam, “Software pipelining: An effective scheduling technique for VLIW machines”, Proc. of the ACM SIGPLAN Conf. on Programming Languages Design and Implementation, Atlanta, June 1988, pp. 318–328.

    Google Scholar 

  56. C. Leiserson and J. Saxe, “Optimizing synchronous systems”, J. of VLSI and Computer Systems, vol. 1, pp. 41–67, 1983.

    MATH  Google Scholar 

  57. H.-D. Lin and D.G. Messerschmitt, “Finite state machine has unlimited concurrency”, IEEE Trans. on Circuits and Systems, vol. 38, pp. 465–475, May 1991.

    Article  Google Scholar 

  58. G. Long, F. Ling, and J.G. Proakis “The LMS algorithm with delayed coefficient adaptation”IEEE Trans. Acoust.,Speech, Signal Processing, vol. 37, no. 9, pp. 1397–1405, Sept. 1989.

    Article  MATH  Google Scholar 

  59. G. Long, F. Ling, and J.G. Proakis, “Corrections to ”The LMS algorithm with delayed coefficient adaptation“”, IEEE Trans. Signal Processing, vol. 40, no. 1, pp. 230–232, Jan. 1992.

    Article  Google Scholar 

  60. H.H. Loomis and B. Sinha, “High speed recursive digital filter realization”, Circuits, Syst.,Signal Processing, vol. 3, no. 3, pp. 267–294, 1984.

    Article  MATH  Google Scholar 

  61. F. Lu and H. Samueli, “A 60-MBd, 480-Mb/s, 256-QAM decision-feedback equalizer in 1.2/2 CMOS”, IEEE Journal of Solid-State Circuits, vol. 28, pp. 330–338, March 1993.

    Article  Google Scholar 

  62. H. De Man, “Architecture driven synthesis techniques for VLSI implementation of DSP algorithms”, Proceedings of IEEE, pp. 319–335, Feb. 1990.

    Google Scholar 

  63. M. C. McFarland, A. C. Parker, and R. Composano, “The high-level synthesis of digital systems’, Proceedings of IEEE, pp. 301–318, Feb. 1990.

    Google Scholar 

  64. J. G. McWhirter, “Recursive least-squares minimization using a systolic array”Proc. SPIE, vol. 431, Real-Time Signal Processing VI, pp. 105–112,1983.

    Article  Google Scholar 

  65. I. Megory-Cohen, C. M. Melas, M. Hassner, and T. Howell, “An analytical model for magnetic readback pulses”, IBM Res. Rep. RJ5236, July 1986.

    Google Scholar 

  66. T. Meng and D. G. Messerschmitt, “Arbitrarily high sampling rate adaptive filters”, IEEE Trans. on Acoustics, Speech and Signal Proc., vol. 35, pp. 455–470, April 1987.

    Article  Google Scholar 

  67. M.D. Meyer and D.P. Agrawal, “A modular pipelined implementation of a delayed LMS transversal adaptive filter”Proc. 1990 IEEE Int. Symp. Circuits and Systems, New Orleans, pp. 1943–1946.

    Google Scholar 

  68. T. G. Noll, et al, “A pipelined 330 MHz multiplier”, IEEE J. of Solid-State Circuits, vol. 21, no. 3, pp. 411–416, June 1986.

    Article  Google Scholar 

  69. D. A. Padua and M. J. Wolfe, “Advanced compiler organizations for supercomputers”, Communications of the ACM, vol. 29, no. 12, pp. 1184–1201, 1986.

    Article  Google Scholar 

  70. K. K. Parhi and D. G. Messerschmitt, “Concurrent cellular VLSI adaptive filter architectures”, IEEE Trans. on Circuits and Systems, vol. 34, pp. 1141–1151, Oct. 1987.

    Article  Google Scholar 

  71. K.K. Parhi and D.G. Messerschmitt, “Concurrent architectures for two dimensional recursive digital filtering”, IEEE Trans. on Circuits and Systems, vol. 36, pp. 813–829, June 1989.

    Article  Google Scholar 

  72. K.K. Parhi and D.G. Messerschmitt, “Pipeline interleaving and parallelism in recursive digital filters - Part I: Pipelining using scattered look-ahead and decomposition”, IEEE Trans. on Acoustics, Speech and Signal Proc., vol. 37, pp. 1099–1117, July 1989.

    Article  MATH  Google Scholar 

  73. K.K. Parhi and D.G. Messerschmitt, “Pipeline interleaving and parallelism in recursive digital filters - Part II: Pipelined incremental block filtering”IEEE Trans. on Acoustics, Speech and Signal Proc., vol. 37, pp. 1118–1134, July 1989.

    Article  MATH  Google Scholar 

  74. K.K. Parhi, “Algorithm transformation techniques for concurrent proces-sors”, Proceedings of the IEEE, vol. 77, pp. 1879–1895, Dec. 1989.

    Article  Google Scholar 

  75. K. K. Parhi and D. G. Messerschmitt, “Static rate-optimal scheduling of iterative data-flow programs via optimal unfolding”, IEEE Trans. on Comput., vol. 40, no. 2, pp. 178–195, Feb. 1991.

    Article  Google Scholar 

  76. K. K. Parhi, “A systematic approach for the design of digit-serial signal processing architectures”, IEEE Trans. on Circuits and Systems, vol. 38, no. 4, pp. 358–375, April 1991.

    Article  MathSciNet  Google Scholar 

  77. K.K. Parhi, “Pipelining in dynamic programming architectures”, IEEE Trans. on Signal Processing, vol. 39, pp. 1442–1450, June 1991.

    Article  Google Scholar 

  78. K.K. Parhi, “Pipelining in algorithms with quantizer loops”, IEEE Trans. on Circuits and Systems, vol. 38, pp. 745–754, July 1991.

    Article  Google Scholar 

  79. K. K. Parhi, C.-Y. Wang, and A. P. Brown, “Synthesis of control circuits in folded pipelined DSP architectures”, IEEE J. of Solid-state Circuits, vol. 27, no. 1, pp. 29–43, January 1992.

    Article  Google Scholar 

  80. K.K. Parhi, “High-speed VLSI architectures for Huffman and Viterbi decoders”, IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing, vol. 39, pp. 385–391, June 1992.

    Article  Google Scholar 

  81. K. K. Parhi, “Video data format converters using minimum number of registers”, IEEE Trans. on Circuits and Syst. for Video Tech., vol. 2, no. 2, pp. 255–267, June 1992.

    Article  Google Scholar 

  82. K. K. Parhi, “Systematic synthesis of DSP data format converters using life-time analysis and forward-backward register allocation”, IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing, vol. 39, pp. 423–440, July 1992.

    Article  Google Scholar 

  83. N. Park and A. Parker, “Sehwa: A software package for synthesis of pipelines from behavioral specifications”, IEEE Trans. on CAD of IC’s, vol. 7, no. 3, pp. 356–370, 1988.

    Google Scholar 

  84. P. G. Paulin and J. P. Knight, “Force directed scheduling for the behavioral synthesis of ASICs”, IEEE Trans. on CAD of IC’s, vol. 8, no. 6, pp. 661–679, June 1989.

    Google Scholar 

  85. P. Pirsch, “Adaptive intra-interframe DPCM coder”, The Bell Sys. Tech. J., vol. 61, pp. 747–764, May-June 1982.

    Google Scholar 

  86. P. Pirsch, “Design of a DPCM codec for VLSI realization in CMOS technology”, Proceedings of IEEE, vol. 73, no.4, pp. 592–598, April 1985.

    Article  Google Scholar 

  87. M. Potkonjak and J. Rabaey, “Pipelining: Just another transformation”, Proc. of Application Specific Array Processors, Oakland, IEEE Computer Society Press, pp. 163–177, August 1992.

    Google Scholar 

  88. K. J. Raghunath and K. K. Parhi, “Parallel adaptive decision feedback equalizers”, IEEE Trans. on Signal Processing, vol.41, no.5, pp. 1956–1961, May 1993.

    Article  MATH  Google Scholar 

  89. B. R. Rau et al, “Efficient code generation for horizontal architectures: Compiler techniques and architectural support”, Proc. of 9th Int. Symp. on Computer Architecture, 1982.

    Google Scholar 

  90. A. Rothermel, “Realization of a DPCM coder for 13.5 MHz sampling rate in CMOS technology”, IEEE Journal of Solid-State Circuits, vol. SC-22, no.6, pp. 1196–1197, Dec. 1987.

    Article  Google Scholar 

  91. V. P. Sathe and P. P. Vaidyanathan, “Effects of multirate systems on the statistical properties of random signals”, IEEE Trans. on Signal Processing, vol. 41, no. 3, pp. 131–146, Jan. 1993.

    Article  MATH  Google Scholar 

  92. M. Schobinger, B. Zehner, F. Matthiesen, U. Totzek, J. Hartl, and U. Reimann, “A single-chip adaptive DPCM video codec”, IEEE Journal of Solid-State Circuits, vol. 24, no.4, pp. 991–996, August 1989.

    Article  Google Scholar 

  93. M. Schobinger, et al, “CMOS digital adaptive decision feedback equalizer chip for multilevel QAM digital radio modems”, Proc. IEEE Intl’ Symp. Circ. and Syst., pp. 574–557, May 1990.

    Google Scholar 

  94. N.R. Shanbhag and K.K.. Parhi, “A pipelined LMS adaptive filter architecture”, Proc. 25th Asilomar Conf. on Sig., Sys., and Comput., Calif., Nov. 1991, pp. 668–672.

    Google Scholar 

  95. N. R. Shanbhag and K. K. Parhi, “A high-speed architecture for ADPCM coder and decoder”, in Proc. IEEE Intl. Symp on Circuits and Systems, San Diego, May 1992, pp. 1499–1502.

    Google Scholar 

  96. N.R. Shanbhag and K.K. Parhi, “A pipelined adaptive lattice filter architecture: Theory and applications”, Proc. EUSIPCO ‘82, Brussels, Belgium, Aug. 1992, pp. 1057–1060.

    Google Scholar 

  97. N. R. Shanbhag and K. K. Parhi, “A pipelined differential vector quantizer architecture for real-time video applications”, in Proc. IEEE Workshop on Visual Signal Processing and Communications, Raleigh, North Carolina, Sept. 1992, pp. 9–14.

    Google Scholar 

  98. N. R. Shanbhag and K. K. Parhi, “A pipelined adaptive differential vector quantizer for low-power speech coding applications”, IEEE Trans. on Circuits and Systems, vol. 40, pp. 347–349, May 1993.

    Article  MATH  Google Scholar 

  99. N. R. Shanbhag and K. K. Parhi, “A pipelined adaptive lattice filter architecture”, IEEE Trans. on Signal Processing, vol. 41, pp. 1925–1939, May 1993.

    Article  MATH  Google Scholar 

  100. N. R. Shanbhag and K. K. Parhi, “Roundoff error analysis of the pipelined ADPCM coder”, in Proc. IEEE Intl. Symp. on Circuits and Systems, Chicago, IL, May 1993, pp. 886–889.

    Google Scholar 

  101. N. R. Shanbhag and K. K. Parhi, “Pipelined adaptive DFE architectures”, in SPIE Advanced Signal Processing Algorithms, Architectures, and Implementations IV, vol. 2027, San Diego, CA, July 1993, pp. 134–145.

    Google Scholar 

  102. N. R. Shanbhag and K. K. Parhi, “VLSI implementation of a 100 MHz pipelined ADPCM codec chip”, in Proc. IEEE VLSI Signal Processing Workshop, Veldhoven, The Netherlands, Oct. 1993, pp. 114–122.

    Google Scholar 

  103. N. R. Shanbhag and K. K. Parhi, “A Pipelined Kalman Filter Architecture”, in Proc. 27th Asilomar Conference on Cir., Sys. and Comp., Pacific Grove, CA, 1993, pp. 1225–1229.

    Google Scholar 

  104. N. R. Shanbhag and K. K. Parhi, “Relaxed Look-ahead pipelined LMS adaptive filters and its application to ADPCM coder”, IEEE Trans. on Circuits and Systems, vol. 40(12), pp. 753–766, Dec. 1993.

    Article  Google Scholar 

  105. S. G. Smith and P. B. Denyer, Serial Data Computation, Norwell, MA: Kluwer Academic Press, 1988.

    Google Scholar 

  106. H. R. Srinivas and K. K. Parhi, “High-speed VLSI arithmetic processor architectures using hybrid number representation”, J. of VLSI Signal Processing, vol.4, pp. 177–198 (1992).

    Article  Google Scholar 

  107. S. Theodoridis, “Pipeline architecture for block adaptive LS FIR filtering and prediction”, IEEE Trans. on Acoustics, Speech and Signal Proc., vol. 38, pp. 81–90, Jan. 1990.

    Article  MathSciNet  Google Scholar 

  108. B. Widrow el al., “Adaptive noise cancelling: Principles and applications”, Proc. IEEE, vol. 63, pp. 1692–1716, Dec. 1975.

    Article  Google Scholar 

  109. B. Widrow et al., “Stationary and non-stationary learning characteristics of the LMS adaptive filter”, Proc. IEEE, vol. 64, pp. 1151–1162, Aug. 1976.

    Article  MathSciNet  Google Scholar 

  110. M. E. Wolf and M. S. Lam, “A loop transformation theory and an algorithm to maximize parallelism”, IEEE Trans. on Parallel and Distributed Systems, vol. 2, no. 4, pp. 452–471, 1991.

    Article  Google Scholar 

  111. J. Yuan and C. Svensson, “High-speed CMOS circuit technique”, IEEE Journal of Solid-State Circuits, vol. 24, no. 1, pp. 62–70, Feb. 1989.

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. AT&T Bell Laboratories, Murray Hill, New Jersey, USA

    Naresh R. Shanbhag

  2. University of Minnesota, Minneapolis, Minnesota, USA

    Keshab K. Parhi

Authors
  1. Naresh R. Shanbhag
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Keshab K. Parhi
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

Copyright information

© 1994 Springer Science+Business Media New York

About this chapter

Cite this chapter

Shanbhag, N.R., Parhi, K.K. (1994). References. In: Pipelined Adaptive Digital Filters. The Springer International Series in Engineering and Computer Science, vol 274. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-2678-0_10

Download citation

  • DOI: https://doi.org/10.1007/978-1-4615-2678-0_10

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4613-6151-0

  • Online ISBN: 978-1-4615-2678-0

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation