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Timing Aspects of CMOS VLSI Circuits

  • F. P. M. Beenker
  • R. G. Bennetts
  • A. P. Thijssen
Part of the Frontiers in Electronic Testing book series (FRET, volume 3)

Abstract

In modern VLSI circuits timing design and timing verification have become serious design problems. In submicron digital integrated circuits the switching speed of the gates tends to be about 0.1 – 0.2 ns. Due to the increase in speed, the physical design of a circuit is no longer a low level electronic design problem. The logic designer is increasingly confronted with physical effects that have a negative influence on the robustness and noise immunity of the circuit under design. This chapter discusses some timing related problems that influence the logic design level as well as the physical design level.

Keywords

Propagation Delay Noise Immunity Logic Level Combinational Logic Clock Period 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media Dordrecht 1995

Authors and Affiliations

  • F. P. M. Beenker
    • 1
  • R. G. Bennetts
    • 2
  • A. P. Thijssen
    • 3
  1. 1.Philips Medical SystemsThe Netherlands
  2. 2.Synopsys, Inc.The Netherlands
  3. 3.TU DelftThe Netherlands

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