Timing Aspects of CMOS VLSI Circuits
In modern VLSI circuits timing design and timing verification have become serious design problems. In submicron digital integrated circuits the switching speed of the gates tends to be about 0.1 – 0.2 ns. Due to the increase in speed, the physical design of a circuit is no longer a low level electronic design problem. The logic designer is increasingly confronted with physical effects that have a negative influence on the robustness and noise immunity of the circuit under design. This chapter discusses some timing related problems that influence the logic design level as well as the physical design level.
KeywordsPropagation Delay Noise Immunity Logic Level Combinational Logic Clock Period
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