Stack-Based Single-Pass Cache Simulation

  • Thomas M. Conte


Memory systems composed of cache memories are so crucial to high-performance computer architecture design that performance evaluation of cache memories has received phenomenal attention. In 1991, Smith catalogued 487 technical papers and reports that dealt with some aspect of caching [11]. This chapter and the following chapter address the problem of simulating cache-based memory systems, To do this optimally requires measurement of the performance of a large number of cache designs. This process is called memory system prototyping here, since this process uses software to construct a prototype memory system. The performance of the prototype is then tested for a set of benchmarks. This software performance evaluation process must be fast yet accurate. A fast method is important so that memory address traces from long-running benchmarks can be used to explore a large design space of potential prototypes.




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  1. [1]
    A. Agarwal, M. Horowitz, and J. Hennessy, “An analytical cache model,” ACM Trans. Computer Systems, vol. 7, pp. 184–215, May 1989.CrossRefGoogle Scholar
  2. [2]
    J. Archibald and J.-L. Baer, “Cache coherence protocols: Evaluation using a multiprocessor simulation model,” ACM Trans. Comput. Sys., vol. 4, pp. 273–298, Nov. 1986.CrossRefGoogle Scholar
  3. [3]
    T. H. Cormen, C. E. Leiserson, and R. L. Rivest, Introduction to Algorithms. Cambridge, MA: McGraw-Hill (MIT Press), 1990.MATHGoogle Scholar
  4. [4]
    T. M. Conte, “Systematic computer archiecture prototyping,” Ph.D. dissertation, Department of Electrical and Computer Engineering, University of Illinois, Urbana, IL, 1992.Google Scholar
  5. [5]
    I. J. Haikala, “Cache hit ratios with geometric task switch intervals,” in Proc. 11th Ann. Int’l Symp. Computer Architecture, (Ann Arbor, MI), pp. 364–371, June 1984.Google Scholar
  6. [6]
    M. D. Hill and A. J. Smith, “Evaluating associativity in CPU caches,” IEEE Trans. Comput., vol. C-38, pp. 1612–1630, Dec. 1989.CrossRefGoogle Scholar
  7. [7]
    W. W. Hwu and T. M. Conte, “The susceptibility of programs to context switching,” IEEE Transactions on Computers, vol. C-43, no. 9, pp. 993–1003, Sep. 1994.Google Scholar
  8. [8]
    K. R. Kaplan and R. O. Winder, “Cache-based computer systems,” Computer, vol. 6, pp. 30–36, Mar. 1973.CrossRefGoogle Scholar
  9. [9]
    R. L. Mattson, J. Gercsei, D. R. Slutz, and I. L. Traiger, “Evaluation techniques for storage hierarchies,” IBM Syst. J., vol. 9, no. 2, pp. 78–117, 1970.CrossRefGoogle Scholar
  10. [10]
    A. J. Smith, “Cache memories,” ACM Computing Surveys, vol. 14, no. 3, pp. 473–530, 1982.CrossRefGoogle Scholar
  11. [11]
    A. J. Smith, “A second bibliography on cache memories,” Comput. Architecture News, vol. 19, pp. 138–153, June 1991.CrossRefGoogle Scholar
  12. [12]
    J. G. Thompson, Efficient analysis of caching systems, Ph.D. dissertation, Computer Science Division, University of California, Berkeley, CA, Oct. 1987. Report No. UCB/CSD 87/374.Google Scholar
  13. [13]
    I. L. Traiger and D. R. Slutz, “One-pass techniques for the evaluation of memory hierarchies,” IBM Research Report RJ 892, IBM, San Jose, CA, July 1971.Google Scholar
  14. [14]
    W.-H. Wang and J.-L. Baer, “Efficient trace-driven simulation methods for cache performance analysis,” ACM Trans. Comput. Sys., vol. 9, pp. 222–241, Aug. 1991.CrossRefGoogle Scholar
  15. [15]
    W. Y. Chen, P. P. Chang, T. M. Conte and W. W. Hwu, “The effect of code expanding optimizations on instruction cache design,” IEEE Transactions on Computers, vol. C-42, no. 9, pp. 1045–1057, Sep. 1993.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media New York 1995

Authors and Affiliations

  • Thomas M. Conte
    • 1
  1. 1.Department of Electrical and Computer EngineeringUniversity of South CarolinaColumbiaUSA

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