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Mapping Combinational Logic

  • Rajeev Murgai
  • Robert K. Brayton
  • Alberto Sangiovanni-Vincentelli
Part of the The Springer International Series in Engineering and Computer Science book series (SECS, volume 324)

Abstract

An important problem in synthesis is to minimize the cost of a design, where the cost is measured by the number of chips needed. This includes the routing considerations within and pin constraints of a chip. Since it is difficult to incorporate all these factors during synthesis, and only limited success has been achieved so far, for instance, in combining synthesis and routability [82], we approximate this cost by the number of blocks needed. Minimizing the number of blocks may be an overkill if the design fits easily on a chip after a simple straightforward mapping. However, consider the situation when the design just exceeds the capacity of the chip. A good synthesis tool may be able to fit the circuit on one chip. In addition, leaving as many blocks unused as possible enables the designer to use the unused logic for improving the properties of the design. Also, as we will show in Chapter 7, minimizing the number of blocks helps in reducing the circuit delay in a placed and routed implementation of the circuit. This is because the blocks can be placed close to each other, reducing the wiring delays considerably. However, as we saw in the last chapter, minimizing the number of blocks is a difficult problem.

Keywords

Equivalence Class Boolean Network Decomposition Tree Primary Input Partial Collapse 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 1995

Authors and Affiliations

  • Rajeev Murgai
    • 1
  • Robert K. Brayton
    • 2
  • Alberto Sangiovanni-Vincentelli
    • 2
  1. 1.Fujitsu Laboratories of America, Inc.USA
  2. 2.University of CaliforniaBerkeleyUSA

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