Abstract
When faced with the task of designing the next generation processor, the designers of company A first come up with a system description of the processor. It includes detailed description of the instruction set, the interface with the external world, design objectives and constraints, etc. Then, using years of expertise in integrated-circuit design, they produce an implementation that meets the design objectives. In order to verify that the implementation is functionally correct (for example, on fetching.and executing an ADD instruction, the correct sum is produced), sequences of input values are applied, and it is checked if the desired outputs are generated. Very likely, the processor is a huge and complex design, and so cannot be tested exhaustively. After achieving a reasonable degree of confidence in the correctness, the designers send the design for fabrication. In due time, say a month, the chip comes back from the foundry and is tested again to verify that it works as expected. This time it is much faster to simulate the same set of test vectors, so many more can be used and more functionality can be tested for. If the chip fails, it is due to either a manufacturing defect, in which case the chip is discarded, or the non-exhaustive testing done earlier on. If the latter, the faulty part of the circuit is identified and fixed and the modified design is resent for fabrication.
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© 1995 Springer Science+Business Media New York
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Murgai, R., Brayton, R.K., Sangiovanni-Vincentelli, A. (1995). Introduction. In: Logic Synthesis for Field-Programmable Gate Arrays. The Springer International Series in Engineering and Computer Science, vol 324. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-2345-1_1
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DOI: https://doi.org/10.1007/978-1-4615-2345-1_1
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