Modeling Multiple Driver Net Delay in Simulation

Abstract

With advances in IC technology and performance have come requirements for additional and more detailed timing analyses. Historically, the effect on timing of the design interconnect (particularly transmission delay) has not represented a significant factor at the IC level. However, as technology pushes below the 1-micron barrier, it is expected that these interconnect factors will no longer be ignored. The timing delay analysis (simulation) required by many ASIC foundries for sign-off will likely require the inclusion of interconnect (wire) delays.

The inclusion of wire delays in simulation is non-trivial from the modeler’s perspective. There is often no defined language construct for the specification of wire delay. The wire delay behavior must be explicitly coded, either as a part of the behavior of leaf components or using special ‘wire’ components. It is simpler (at the netlist level) if the wire delay is included in the leaf (cell) models. However, this approach is generally limited to single-driver interconnects. This paper reviews the requirements associated with modeling wire delay and presents a general-purpose wire delay component model that can support both single- and multi-driver wire delays.