Abstract
This article describes and analyzes the basis of VHDL-A language design: VHDL-A design objectives. Built from user requirements, VHDL-A design objectives specify a set of concrete goals and constraints that VHDL-A language design must meet. In this paper, we categorize design objectives into several groups: language scope, structure description mechanism, behavior description mechanism, and mixed-mode simulation support. We then justify each design objective, and describe various engineering tradeoffs behind each design objective. In addition, the advantages and challenges of building an analog hardware description language on top of VHDL are also discussed.
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© 1995 Springer Science+Business Media Dordrecht
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Shi, CJ.R., Vachoux, A. (1995). VHDL-A Design Objectives And Rationale. In: Bergé, JM., Levia, O., Rouillard, J. (eds) Modeling in Analog Design. Current Issues in Electronic Modeling, vol 2. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-2333-8_1
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DOI: https://doi.org/10.1007/978-1-4615-2333-8_1
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