Abstract
Since the dominant component of power consumption for a properly designed CMOS circuit is proportional to the square of the supply voltage, operating circuits at the lowest voltage is the key to minimizing the energy consumed per operation. However, the individual circuit elements run slower at lower supply voltages (Figure 3.25) and this must be compensated for through appropriate architectural design. One important class of applications are those which have no advantage in exceeding a bounded computation rate, as found in real-time signal processing. The strategies presented in this chapter also have some applicability to the maximum throughput situation of general purpose computing though additional system level trade-offs must be made.
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References
H.B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley, Menlo Park, CA, 1990.
T. Bell, “Incredible shrinking computers,” IEEE Spectrum, pp. 37–43, May 1991.
J. B. Burr and A. M. Peterson, “Energy Considerations in Multichip Module-based Multiprocessors,” ICCD, pp. 593–600, 1991.
A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, “Low-power digital CMOS design, ” IEEE Journal of Solid State Circuits, pp. 473–484, April 1992.
D. Dahle, “Designing High Performance Systems to Run from 3.3V or Lower Sources,” Silicon Valley Personal Computer Conference, pp. 685–691, 1991.
B. Davari et al., “A High Performance 0.25μm CMOS Technology,” IEEE IEDM, pp. 56–59, 1988.
M. Kakumu and M Kinugawa, “Power-Supply Voltage Impact on Circuit Performance for Half and Lower Submicrometer CMOS LSI,” IEEE Transactions on Electron Devices, Vol 37, No. 8, pp. 1902–1908, August 1990.
C. Sodini, P.K. Ko, and J. L. Moll, “The Effect of High Fields on MOS Device and Circuit Performance Devices,” IEEE Transactions on Electron Devices, vol. ED-31, pp. 1386–1393, Oct 1984.
R.K. Watts (ed.), Submicron Integrated Circuits, John Wiley & Sons, NY, 1989.
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© 1995 Springer Science+Business Media New York
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Chandrakasan, A.P., Brodersen, R.W. (1995). Voltage Scaling Approaches. In: Low Power Digital CMOS Design. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-2325-3_4
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DOI: https://doi.org/10.1007/978-1-4615-2325-3_4
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