Code Generation for Transport Triggered Architectures
Transport triggered architectures (TTAs) form a class of architectures which are programmed by specifying data transports between function units. As side effect of these data transports these function units perform operations. Making these data transports visible at the architectural level contributes to the flexibility and scalability of processors. Furthermore it enables several extra code scheduling optimizations. These properties make TTAs very suitable for being applied for embedded processors.
In this article we discuss TTAs, and explain how to generate efficient code for these architectures. The compiler must exploit the available instruction level parallelism inside applications by scheduling as many useful data transports per cycle as the architecture permits. The flexibility and scalability of TTAs will be demonstrated by focusing on a particular algorithm, the minimum cost contour detection algorithm. This algorithm is e.g. used in medicine to perform real-time contour detection of the heart in an echocardiogram. Different processor options are researched for this algorithm. Results of generated code will be discussed with respect to costs, performance and code size.
KeywordsFunction Unit Basic Block Data Transport Result Move Pareto Point
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