Conclusions

Abstract

The increasing impact of short-channel devices and interconnect parasitics on circuit delay and waveform shapes has greatly increased the gap between logic simulation and circuit simulation. Logic simulation is no longer capable of accounting for the effects of interconnect parasitics on the nonlinear behavior of modern gates. On the other hand, the increased netlist size to account for interconnect parasitics has made circuit simulation impractical. Thus, the need for increasingly powerful macromodeling techniques is growing. Macromodeling techniques which can account for secondary gate effects as well as interconnect parasitic effects are needed for commercial design verification systems.