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Analog VLSI Building Blocks

  • Bing J. Sheu
  • Joongho Choi
Part of the The Springer International Series in Engineering and Computer Science book series (SECS, volume 304)

Abstract

Since the number of synapses is typically much larger than the numbers of neurons on a VLSI chip, the characteristics of an analog multiplier used for the synapse cell determines the accuracy, the silicon area, and the power consumption of the neuroprocessor chip. Several design issues should be carefully addressed for performance optimization of the synapse cell.

Keywords

Output Neuron Radial Basis Function Neural Network Input Neuron Differential Pair PMOS Transistor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [1]
    J. Choi and B. J. Sheu, “VLSI design of compact and high-precision analog neural network processors,” Proc. IEEE/INNS Inter. Joint Conf. Neural Networks, vol. 2, pp. 637–641, Baltimore, MD. July, 1992.Google Scholar
  2. [2]
    B. Johnson, T. Quarles, A. R. Newton, D. O. Perderson, and A. Sagiovanni-Vincentelli, SPICE3 Version 3E1 Users Guide, Department of Electrical Engineering and Computer Science, University of California, Berkeley, Apr. 1991.Google Scholar
  3. [3]
    B. J. Sheu and C. Hu, “Switched-induced error voltage on a switched-capacitor,” IEEE Jour. Solid-State Circuits, vol. 19, no. 4, pp. 519–525, Aug. 1984.CrossRefGoogle Scholar
  4. [4]
    C. Eichenberger and W. Guggenbühl, “Dummy transistor compensation of analog MOS switches,” IEEE Jour. Solid-State Circuits, vol. 24, no. 4, pp. 1143–1146, Aug. 1989.CrossRefGoogle Scholar
  5. [5]
    S. Satyanarayana, Y. P. Tsividis, and H. P. Graf, “A reconfigurable VLSI neural network,” IEEE Jour. Solid-State Circuits, vol. 27, pp. 67–81, Jan. 1992.CrossRefGoogle Scholar
  6. [6]
    T. Morishita, Y. Tamura, and T. Otsuki, “A BiCMOS analog neural network with dynamically updated weights,” Tech. Digest IEEE Inter. Solid-State Circuits Conference, pp. 142–143, San Francisco, CA, Feb. 1990.Google Scholar
  7. [7]
    J. Choi, S. H. Bang, and B. J. Sheu, “A programmable analog VLSI neural network processor for communication receivers,” IEEE Trans. Neural Networks, vol. 4, no. 3, pp. 484–495, May 1993.CrossRefGoogle Scholar
  8. [8]
    B. W. Lee and B. J. Sheu, Hardware Annealing in Analog VLSI Neuro-computing, Kluwer Academic Publisher: Boston, MA, 1991.CrossRefGoogle Scholar
  9. [9]
    R. Gregorian and G. C. Temes, Analog MOS Integrated Circuits for Signal Processing, John Wiley and Sons: New York, NY, 1986.Google Scholar
  10. [10]
    M. Banu and Y. Tsividis, “Floating voltage-controlled resistors in CMOS technology,” Electronics Letters, vol. 18, pp. 678–679, 1982.CrossRefGoogle Scholar
  11. [11]
    A. Mortara, E. A. Vittoz, “A communication architecture tailored for analog VLSI artificial neural networks: intrinsic performance and limitations,” IEEE Trans. on Neural Networks, vol. 5, no. 3, pp. 459–466, May 1994.CrossRefGoogle Scholar
  12. [12]
    R. L. Lippman, “A critical overview of neural network pattern classifier,” Proc. IEEE Neural Networks for Signal Processing Workshop, pp. 266–275, Princeton, NJ, 1991.Google Scholar
  13. [13]
    A. L. Dajani, M. Kamel, and M. I. Elmasry, “Single layer potential function neural network for unsupervised learning,” Proc. IEEE/INNS Inter. Joint Conf. Neural Networks, vol. 2, pp. 273–278, San Diego, CA, 1990.CrossRefGoogle Scholar
  14. [14]
    P. Burrascano, “A norm selection criterion for the generalized Delta rule,” IEEE Trans. Neural Networks, vol. 2, no. 1, pp. 125–130, Jan. 1991.CrossRefGoogle Scholar
  15. [15]
    S. Lee and R. Kil, “Multilayer feedforward potential function network,” Proc. IEEE/INNS Inter. Joint Conf. Neural Networks, vol. 1, pp. 161–172, San Diego, CA, July 1988.Google Scholar
  16. [16]
    J. Platt, “A resource-allocating neural network for function interpolation,” Neural Computation, vol. 3, no. 2, pp. 213–225, Summer, 1991.MathSciNetCrossRefGoogle Scholar
  17. [17]
    S. Renais and R. Rohwer, “Phoneme classification experiments using radial basis functions,” Proc. IEEE/INNS First Inter. Joint Conf. Neural Networks, vol. 1, pp. 461–467, San Diego, CA, July 1987.Google Scholar
  18. [18]
    T. Poggio and F. Girosi, “Networks for approximation and learning,” IEEE Proceedings, vol. 78, no. 9, pp. 1481–1497, Sep. 1990.CrossRefGoogle Scholar
  19. [19]
    S. S. Watkins, P. M. Chau, and R. Tawel, “A radial basis function neurocomputer implemented with analog VLSI circuits,” Proc. IEEE/INNS Inter. Joint Conf. Neural Networks, vol. 2, pp. 607–612, Baltimore, MD, June 1992.Google Scholar
  20. [20]
    C. A. Mead, Analog VLSI and Neural Systems, Addison-Wesley Publishing Company: Reading, MA, 1989.MATHCrossRefGoogle Scholar
  21. [21]
    P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 2nd Ed., John Wiley and Sons: New York, NY, 1993.Google Scholar
  22. [22]
    C. Tomovich, “MOSIS-a gate way to silicon,” IEEE Circuits and Systems Magazine, vol. 4, pp. 22–23, Mar. 1988.Google Scholar
  23. [23]
    G. Lewicki, “Foresight: a fast turn-around and low cost ASIC prototyping alternatives,” Proc. IEEE ASIC Seminar and Exhibit, pp. p.6–8.1/8.2, Rochester, NY, Sep. 1990.Google Scholar
  24. [24]
    P. W. Hollis and J. J. Paulos, “Artificial neural networks using MOS analog multiplier,” IEEE Jour. Solid-State Circuits, vol. 25, pp. 849–855, June 1990.CrossRefGoogle Scholar
  25. [25]
    L. Lemaitre, M. J. Patyra, D. Mlynek, “Analysis and design of CMOS fuzzy logic controller in current mode,” IEEE Jour. of Solid-State Circuits, vol. 29, no. 3, pp. 317–322, Mar. 1994.CrossRefGoogle Scholar
  26. [26]
    L. Lemaitre, M. J. Patyra, D. Mlynek, “Synthesis and design automation of analog fuzzy logic VLSI circuits,” Proc. of IEEE Symposium on Multiple-Valued Logic, pp. 74–79, Sacramento, CA, May 1993.Google Scholar
  27. [27]
    J. Ramirez-Angulo, “Building blocks for fuzzy processors,” IEEE Circuits and Devices Magazine, vol. 10, no. 4, pp. 48–50, July 1994.Google Scholar
  28. [28]
    T. Yamakawa, “A fuzzy inference engine in nonlinear mode and its application to a fuzzy logic control,” IEEE Trans. on Neural Networks, vol. 4, no. 3, pp. 496–522, May 1993.CrossRefGoogle Scholar
  29. [29]
    J. W. Fattaruso, S. S. Mahan-Shetti, J. Brock-Barton, “A fuzzy logic inference processor,” Third Conf. on Industrial Fuzzy Control and Intelligence Systems, pp. 210–214, Houston, TX, Dec. 1993.Google Scholar

Copyright information

© Springer Science+Business Media New York 1995

Authors and Affiliations

  • Bing J. Sheu
    • 1
  • Joongho Choi
    • 2
  1. 1.University of Southern CaliforniaUSA
  2. 2.IBM Thomas J. Watson Research CenterUniversity of Southern CaliforniaUSA

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