Clock Recovery and Data Retiming IC: Circuit Design and Simulation Results

Abstract

In this final chapter we return to system-level issues and blend them with circuit design constraints to produce a clock-recovery and data retiming IC. We will not present a detailed circuit, but rather outline the design procedure and give preliminary simulation results, both at the system-and transistor-level. As was discussed at the end of chapter 5, characterization of clock recovery circuits by simulation is difficult for two primary reasons. First, the input signal consists of random data plus noise; therefore, typical performance measures are based on statistical techniques, which require several data samples. Second, the clock recovery circuit is narrow-band compared to the data-rate, requiring thousands, or even millions, of bit-periods to be observed before the clock phase is altered. Nonetheless, simulation can predict the maximum speed of operation and is useful in optimizing the circuits dynamic response. Several aspects of a clock recovery system have been simulated, and some of the results will be presented in this chapter. We will first present system-level simulations, which are used to evaluate various architectures under ideal conditions. Then we will show how these architectures can be implemented as ICs and give preliminary circuit simulation results. ¹