A Deterministic Finite-State Model for VHDL

  • Gert Döhmen
  • Ronald Herrmann
Part of the The Kluwer International Series in Engineering and Computer Science book series (SECS, volume 307)

Abstract

In this chapter we present a method for translating VHDL ’87 into deterministic finitestate models. The method can handle those aspects of VHDL which have a finite representation and obtains the semantics defined in the IEEE standard. The model can be used to interface VHDL with BDD-based verification tools.

Keywords

Assure 

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Copyright information

© Springer Science+Business Media Dordrecht 1995

Authors and Affiliations

  • Gert Döhmen
    • 1
  • Ronald Herrmann
    • 1
  1. 1.Integrierte Hardware-Software SystemeOFFISGermany

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