A Deterministic Finite-State Model for VHDL
In this chapter we present a method for translating VHDL ’87 into deterministic finitestate models. The method can handle those aspects of VHDL which have a finite representation and obtains the semantics defined in the IEEE standard. The model can be used to interface VHDL with BDD-based verification tools.
KeywordsComposition Operator Auxiliary Function Data Space Sequential Statement Input Port
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