A Functional Semantics for Delta-Delay VHDL Based on Focus

Abstract

This tutorial paper gives a functional semantics for delta-delay VHDL, i.e. VHDL restricted to zero-delay signal assignments. In combination with the sequential statements zero-delay signal assignment is sufficient to generate the full algorithmic expressibility of VHDL. The restriction is useful for a formal semantics of VHDL aimed at higher levels of abstraction where real, absolute, and precise timing often is painful if not impossible to prescribe.

The approach employs the functional specification methodology Focus which is based on the concept of streams and stream-processing functions. It advocates a three-level semantics reflecting VHDL’s three syntactic levels of expressions, statements, and processes.

... ‘It’s long,’ said the Knight, ‘but very, VERY beautiful. Everybody that hears me sing it — either it brings the TEARS into their eyes, or else — ... ’

Lewis Carroll, Alice Through the Looking Glass