Abstract
With Verilog-1995, the size of Verilog vectors can be declared using Verilog parameters, which are run-time constants. A “parameterized” module can be redefined for each instance of that module. Verilog syntax requires that the parameter be declared prior to using it as part of a port declaration or data type declaration.
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© 2002 Springer Science+Business Media New York
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Sutherland, S. (2002). Module port parameter lists. In: Verilog — 2001. The Springer International Series in Engineering and Computer Science, vol 652. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-1713-9_5
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DOI: https://doi.org/10.1007/978-1-4615-1713-9_5
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-5691-2
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