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On-detect pulse error propagation

  • Stuart Sutherland
Part of the The Springer International Series in Engineering and Computer Science book series (SECS, volume 652)

Abstract

In the Verilog standard, a glitch is referred to as a pulse, and refers to a sequence of input logic changes that cause a second output change to be scheduled before the first change has actually occurred. As a simple example, assume that a buffer module has a timing path from the a input to the y output, specified as follows:

Keywords

Computer Hardware Propagation Background Output Event Path Delay Timing Path 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Copyright information

© Springer Science+Business Media New York 2002

Authors and Affiliations

  • Stuart Sutherland
    • 1
  1. 1.Sutherland HDL, Inc.USA

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