On-detect pulse error propagation
Part of the
The Springer International Series in Engineering and Computer Science
book series (SECS, volume 652)
In the Verilog standard, a glitch is referred to as a pulse, and refers to a sequence of input logic changes that cause a second output change to be scheduled before the first change has actually occurred. As a simple example, assume that a buffer module has a timing path from the a input to the y output, specified as follows:
KeywordsComputer Hardware Propagation Background Output Event Path Delay Timing Path
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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