Skip to main content

Part of the book series: The Springer International Series in Engineering and Computer Science ((SECS,volume 610))

  • 100 Accesses

Abstract

There is a growing consensus that energy consumption is becoming an important issue for a wide variety of systems. Two factors fuel these trends: (1) increasing use of embedded and portable computing devices in everyday life, and (2) very high power dissipation levels reached by current state-of-the-art processors. Consequently, recent years have witnessed a host of studies that address the problem of reducing the energy consumption.

Unfortunately, most of the energy-oriented studies are from design automation and architecture domain, and only very recently software-based approaches to the problem have appeared in research papers. In this chapter, we take an early step in evaluating the energy consumption of a selected set of benchmarks from three different application domains. Setting off with the observation that memory energy constitutes a large percentage of overall energy budget, we focus on memory energy behavior and observe the variations in cache and memory energies under different cache configurations.

This project was funded in part by the Pittsburgh Digital Greenhouse through a grant from the Commonwealth of Pennsylvania, Department of Community and Economic Development and NSF CCR-0073419.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 169.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 219.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 219.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. G. Albera and R. I. Bahar, “Power and performance tradeoffs using various cache configurations,” in Proc. Power Driven Micro-architecture Workshop in conjunction with ISCA’98, 1998.

    Google Scholar 

  2. M. B. Kamble and K. Ghose, “Energy-efficiency of VLSI caches: A comparative study,” in Proc. of International Conference on VLSI Design, pp. 261–267, 1997.

    Chapter  Google Scholar 

  3. K. Ghose and M. Kamble, “Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation,” in Proceedings of International Symposium on Low Power Electronics and Design, pp. 70–75, 1999.

    Google Scholar 

  4. J. Kin et. al., “The filter cache: An energy efficient memory structure,” in Proc. of MICRO’97, December 1997.

    Google Scholar 

  5. K. Roy and M. C. Johnson, “Software design for low power,” in Low Power Design in Deep Sub-micron Electronics, pp. 433–459, Kluwer Academic Press. October 1996, ed. J. Mermet and W. Nebel.

    Google Scholar 

  6. V. Tiwari, S. Malik, A. Wolfe, and T. Lee, “Instruction level power analysis and optimization of software,” Journal of VLSI Signal Processing Systems, vol. 13, August 1996.

    Google Scholar 

  7. C. Ellis, A. Lebeck, and A. Vahdat, “System support for energy management in mobile and embedded workloads: A white paper,” in http://www.cs.duke.edu/carla/research/whitepaper.pdf.

  8. Y.-H. Lu, L. Benini, and G. D. Micheli, “Operating-system directed power reduction,” in Proceedings of International Symposium on Low Power Electronics and Design, 2000.

    Google Scholar 

  9. F. Catthoor, S. Wuytack, E. D. Greef, F. Balasa, L. Nachtergaele, and A. Vandecappelle, Custom memory management methodology — exploration of memory organization for embedded multimedia system design. Springer Science+Business Media New York, 1998.

    Google Scholar 

  10. C. Lee, M. Potkonjak, and W. H. Mangione-Smith, “Mediabench: A tool for evaluating and synthesizing multimedia and com munications systems,” in Proceedings of 30th Annual International Symposium on micro architecture, pp. 330–335, 1997.

    Google Scholar 

  11. C. Ballinger, “Relevance of the tpc-d benchmark queries: The questions you ask every day,” in http://www.tpc.org/articles/articleshome.html.

  12. M. C. Toburen, “Power analysis and instruction scheduling for reduced di/dt in the execution core of high-performance microprocessors,” tech. rep., MS. Thesis, Computer Engineering, North Carolina State University, 1999.

    Google Scholar 

  13. W. Ye., “Architectural level power estimation and experimentation,” tech. rep., Ph.D. Thesis, Comp. Sci. and Eng., The Pennsylvania State University, 1999.

    Google Scholar 

  14. M. Kamble and K. Ghose, “Analytical energy dissipation models for low power caches,” in Proceedings of International Symposium on Low Power Electronics and Design, pp. 143–148, 1997.

    Chapter  Google Scholar 

  15. S. Wilton and N. Jouppi, “An enhanced access and cycle time model for on-chip caches,” Tech. Rep. 93/5, DEC WRL Research report, 1994.

    Google Scholar 

  16. W.-T. Shiue and C. Chakrabarti, “Memory exploration for low power, embedded systems,” Tech. Rep. CLPE-TR-9–1999–20, Arizona State University, 1999.

    Google Scholar 

  17. M. E. Wolf, D. E. Maydan, and D.-K. Chen, “Combining loop transformations considering caches and scheduling,” in Proc. Int’l Symp. Microarchitecture, pp. 274–286, 1996.

    Google Scholar 

  18. A. Chandrakasan and R. Brodersen, Low Power Digital CMOS Design. Springer Science+Business Media New York, 1995.

    Google Scholar 

  19. C.-L. Su and A. M. Despain, “Cache design trade-offs for power and performance optimization: a case study,” in Proc. ISLPED, pp. 63–68, 1995.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2001 Springer Science+Business Media New York

About this chapter

Cite this chapter

Kim, H.S., Kandemir, M., Vijaykrishnan, N., Irwin, M.J. (2001). Characterization of Memory Energy Behavior. In: John, L.K., Maynard, A.M.G. (eds) Workload Characterization of Emerging Computer Applications. The Springer International Series in Engineering and Computer Science, vol 610. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-1613-2_8

Download citation

  • DOI: https://doi.org/10.1007/978-1-4615-1613-2_8

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4613-5641-7

  • Online ISBN: 978-1-4615-1613-2

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics