Abstract
Logic verification is to check the correct behavior of a given circuit against its specification. This specification can be given in the form of another circuit at some higher level of abstraction or as a description of properties that the circuit is to obey. In this chapter a review of some “classical” approaches for verification is given followed by a discussion of a spectral based technique for equivalence checking [154]. For more detailed surveys of verification methodologies see [31, 79, 88, 99]
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© 2001 Springer Science+Business Media New York
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Thornton, M.A., Drechsler, R., Miller, D.M. (2001). Logic Verification. In: Spectral Techniques in VLSI CAD. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-1425-1_8
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DOI: https://doi.org/10.1007/978-1-4615-1425-1_8
Publisher Name: Springer, Boston, MA
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