Abstract
Fully planarized advanced interconnect structures with copper metallization and ultra low-κ ILDs fabricated by dual damascene patterning currently prevent conventional ICs from being interconnect limited. However, as CMOS scaling and lithography advances reduce the minimum feature size below 50 nm, interconnects will again become a performance limiter and probably a manufacturing cost enhancer. Unlike the situation in the late 80s, new materials and a new patterning process used with an increasing amount of interconnect levels will not be a viable solution. After copper metallization with atomic-scale liners and dielectrics with κ<1.8, conventional approaches are not compatible with the performance needed with sub-50nm devices.
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Borst, C.L., Gill, W.N., Gutmann, R.J. (2002). Future Directions in IC Interconnects and Related Low-κ Ild Planarization Issues. In: Chemical-Mechanical Polishing of Low Dielectric Constant Polymers and Organosilicate Glasses. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-1165-6_8
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DOI: https://doi.org/10.1007/978-1-4615-1165-6_8
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