TRP for Low-Power Scan Testing

  • Krishnendu Chakrabarty
  • Vikram Iyengar
  • Anshuman Chandra
Part of the Frontiers in Electronic Testing book series (FRET, volume 20)

Abstract

Reduction of test data volume and power consumption for scan vectors are two major problems in system-on-a-chip testing. Since static compaction of scan vectors invariably leads to higher power for scan testing, the conflicting goals of low-power scan testing and reduced test data volume appear to be irreconcilable. We tackle this problem by using test data compression to reduce both test data volume and scan power1. In particular, we show that Golomb coding of precomputed test sets leads to significant savings in peak and average power, without requiring either a slower scan clock or blocking logic in the scan cells. We also improve upon prior work on Golomb coding by showing that a separate cyclical scan register is not necessary for pattern decompression.

Keywords

Compaction 

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Copyright information

© Springer Science+Business Media New York 2002

Authors and Affiliations

  • Krishnendu Chakrabarty
    • 1
  • Vikram Iyengar
    • 1
  • Anshuman Chandra
    • 1
  1. 1.Department of Electrical and Computer EngineringDuke UniversityDurham

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