One of the practical difficulties with the processor verification techniques discussed in Chapter 6 is the chasm between what can be verified and the complexity of contemporary commercial designs. The work in this chapter was motivated by the multiple commercial out-of-order processors that appeared in the mid-1990’s [Gwe95, Gwe94b, Gwe94a, Gwe96b]. The distinct features of out-of-order architectures are a challenge for existing verification approaches. First, the extended instruction parallelism in out-of-order architectures results in many potential interactions between executing instructions. The number of interactions makes it difficult to devise an abstraction function. Second, large buffers are used to record and maintain the program order of instructions. This results in a large effective pipeline length.


Register File Reachable State Proof Obligation Instruction Sequence Simulation Relation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media New York 2002

Authors and Affiliations

  • Robert B. Jones
    • 1
  1. 1.Strategic CAD LabsIntel CorporationUSA

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