The chip’s processor core implements the ARM V4 instruction set architecture (ISA) [6.1]. The implementation was derived from an RTL behavioral model (provided by ARM Ltd.) which fixed both the ISA as well as the processor core interface. However, both the custom physical implementation of the core, as well as the rest of the microprocessor design, were fully optimized for energy efficiency.
KeywordsProcessor Core Cache Line Cache Memory Cache System Memory Stage
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- [6.1]Advanced RISC Machines, Ltd., ARM Architecture and Implementation Reference, Document Number ARM-DDI-0100A-I, Feb. 1996.Google Scholar
- [6.2]Advanced RISC Machines, Ltd., ARM 8 Data Sheet, Document Number ARM-DDI-0100A-I, Feb. 1996.Google Scholar
- [6.3]J. Hennessy, D. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann, San Francisco, 1995.Google Scholar
- [6.4]T. Burd, B. Peters, A Power Analysis of a Microprocessor: A Study of an Implementation of the MIPS 3000 Architecture, ERL Technical Report, University of California, Berkeley, 1994.Google Scholar
- [6.5]A. Burstein, Speech Recognition for Portable Multimedia Terminals, Ph.D. Thesis, University of California, Berkeley, Document No. UCB/ERL M97/ 14, 1997.Google Scholar
- [6.6]T. Pering, Energy-Efficient Operating System Techniques, Ph.D. Thesis, University of California, Berkeley, 2000.Google Scholar
- [6.7]Hewlett Packard, CMOS 14TA/B Reference Manual, Document Number #A-5660–7127–3, Jan. 1995.Google Scholar