Case Study: Validating the MAGIC SDM Using a SAR Processor Application
In this chapter we validate that the MAGIC SDM can be used to accomplish the specification and design of a system representative of our ADoI. We choose the RASSP SAR benchmark (cf. §7.1) since it will be a level playing field on which to assess how our MAGIC SDM performs compared to the two main types of SDMs used with COTS MP technologies in our ADoI (cf. §2.2.2). The first type is virtual prototyping (VP), which is the specification and design of a digital system using an executable language such as VHDL. Virtual prototyping was found to be quite unwieldy for larger more complex applications like those found in this ADoI, because simulation runtimes were painfully long, and only those activities near the beginning of the hardware initialization cycle could be explored. For example, in the virtual prototyping of RASSP SAR, only the first 150 milliseconds of a 3-second frame could be simulated [2, 3]. The second type of SDM are deployable CASE frameworks (cf. §220.127.116.11), which have some model continuity and complexity control, but require the developer to commit to a hardware target before starting the design phase, the reverse of what the specification and design process should do.
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