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Flexibility in Logic

  • Ellen Sentovich
  • Daniel Brand
Part of the The Springer International Series in Engineering and Computer Science book series (SECS, volume 654)

Abstract

It is possible to synthesize more efficient implementations if we remove the requirement of preserving local functionality. This can be done to some degree by taking into account the environment of the logic targeted by synthesis. The environment provides flexibility in the choice of functionality. This chapter describes how a designer can specify the environment information, how the environment information can be derived, and how synthesis can take advantage of it.

Keywords

Environment Network Truth Table Boolean Network Target Network Sequential Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [1]
    A. Aziz, F. Balarin, R. Brayton, and A. Sangiovanni-Vincentelli. “Sequential synthesis using SIS,” in Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 612–617, Nov. 1995.Google Scholar
  2. [2]
    K. Bartlett, R. Brayton, G. Hachtel, R. Jacoby, C. Morrison, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang, “Multi-level logic minimization using implicit don’t cares,” IEEE Transactions on Computer-Aided Design, vol. CAD-7, pp. 723–740, June 1988.CrossRefGoogle Scholar
  3. [3]
    F. Berglez, P. Pownall, and R. Humm, “Accelerated ATPG and fault grading via testability analysis,” in International Symposium on Circuits and Systems, pp. 695–698, IEEE, June 1985.Google Scholar
  4. [4]
    D. Brand, “Redundancy and don’t cares in logic synthesis,” IEEE Transactions on Computers, vol. C-32, pp. 947–952, October 1983.MathSciNetCrossRefGoogle Scholar
  5. [5]
    D. Brand, R. A. Bergamaschi, and L. Stok, “Don’t cares in synthesis: Theoretical pitfalls and practical solutions” IEEE Transactions on Computer-Aided Design, vol. CAD-17, pp. 285–304, April 1998.CrossRefGoogle Scholar
  6. [6]
    R. Brayton, “Compatible observability don’t cares revisited,” in Proceedings of the International Workshop on Logic Synthesis, 2001.Google Scholar
  7. [7]
    R. Brayton, G. Hachtel, C. McMullen, and A. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis. Kluwer Academic Publishers, 1984.Google Scholar
  8. [8]
    R. Brayton, G. Hachtel, and A. Sangiovanni-Vincentelli, “Multilevel logic synthesis,” Proceedings of the IEEE, vol. 78, pp. 264–300, Feb. 1990.CrossRefGoogle Scholar
  9. [9]
    R. Brayton and E. Sentovich, “Network hierarchies and node minimization,” IEICE Transactions on Information and Systems, vol. E78-D, pp. 199–208, Mar. 1995.Google Scholar
  10. [10]
    R. Brayton and F. Somenzi, “Boolean relations and the incomplete specification of logic networks,” in Proceedings of the International Conference on VLSI, pp. 231–240, Aug. 1989.Google Scholar
  11. [11]
    R. Brayton and F. Somenzi, “An exact minimizer for Boolean relations,” in Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 316–319, Nov. 1989.Google Scholar
  12. [12]
    D. Bryan, “Redundancy identification and removal,” in Proceedings of the International Workshop on Logic Synthesis, MCNC, 1989.Google Scholar
  13. [13]
    K. T. Cheng, “On removing redundancy in sequential circuits,” in Proceedings of the ACM/IEEE Design Automation Conference, pp. 164–169, ACM/IEEE, 1991.Google Scholar
  14. [14]
    H. Cho, G. D. Hachtel, and F. Somezi, “Redundancy identification and removal based on bdds and implicit state enumeration,” in Proceedings of the International Workshop on Logic Synthesis, 1991.Google Scholar
  15. [15]
    O. Coudert, C. Berthet, and J. Madre, “Verification of synchronous sequential machines based on symbolic execution,” in Automatic Verification Methods for Finite State Systems, pp. 365–373, Springer-Verlag, 1989.Google Scholar
  16. [16]
    M. Damiani and G. DeMicheli, “Recurrence equations and the optimization of synchronous logic circuits,” in Proceedings of the 29th Design Automation Conference, pp. 556–561, June 1992.Google Scholar
  17. [17]
    G. DeMicheli, Synthesis and Optimization of Digital Circuits. McGraw-Hill, Inc., 1994.Google Scholar
  18. [18]
    H. Fujiwara and T. Shimono, “On the acceleration of test generation algorithms,” IEEE Transactions on Computers, vol. 31, pp. 1137–1144, 1983.CrossRefGoogle Scholar
  19. [19]
    A. Ghosh, S. Devadas, and A. Newton, “Heuristic minimization of Boolean relations using testing techniques,” in Proceedings of the International Conference on Computer Design, Sept. 1990.Google Scholar
  20. [20]
    M. A. Iyer and M. Abramovici, “Low-cost redundancy identification for combinational circuits,” in Proceedings of the International Conference on VLSI design, pp. 315–317, IEEE, January 1994.Google Scholar
  21. [21]
    T. Kam, T. Villa, R. Brayton, and A. Sangiovanni-Vincentelli, “A fully implicit algorithm for exact state minimization,” Tech. Rep. Memorandum No. UCB/ERL M93/79, University of California Berkeley, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, CA 94720, Nov. 1993.Google Scholar
  22. [22]
    M. Karnaugh, “The map method for synthesis of combinational logic circuits,” Transactions AIEE, vol. 72, no. 9, pp. 593–599, 1953.MathSciNetGoogle Scholar
  23. [23]
    J. Kim and M. Newborn, “The simplification of sequential machines with input restrictions,” IEEE Transactions on Computers, pp. 1440–1443, Dec. 1972.Google Scholar
  24. [24]
    J. Kim, J. M. Silva, H. Savoj, and K. Sakallah, “Rid-grasp: Redundancy identification and removal using grasp,” in Proceedings of the International Workshop on Logic Synthesis, 1997.Google Scholar
  25. [25] R. P. Kunda, P. Narain, J. A. Abraham, and B. D. Rathi, “Speed up of test generation using high-level primitives,” in Proceedings of the 27th ACM/IEEE Design Automation Conference, (Orlando), pp. 594–599, ACM/IEEE, June 1990.Google Scholar
  26. [26] S. Kundu, L. H. Huisman, I. Nair, V. S. Iyengar, and L. N. Reddy, “A small test generator for large designs,” in Proceedings of the International Test Conference, pp. 30–40, IEEE,Google Scholar
  27. [27]
    W. Kunz and D. K. Pradham, “Recursive learning: A new implication technique for efficient solutions to cad problems — test, verification, and optimization,” IEEE Transactions on Computer-Aided Design, vol. CAD-13, pp. 1143–1158, September 1994.CrossRefGoogle Scholar
  28. [28]
    T Larrabee, “Test pattern generation using boolean satisfiability,” IEEE Transactions on Computer-Aided Design, vol. CAD-11, pp. 4–15, January 1992.CrossRefGoogle Scholar
  29. [29]
    M. Lehman and N. Burla, “Skip techniques for high-speed carry-propagation in binary arithmetic circuits,” IRE Transactions on Electronic Computers, pp. 691–698, December 1961.Google Scholar
  30. [30]
    B. Lin and F. Somenzi, “Minimization of symbolic relations,” in Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 88–91, Nov. 1990.Google Scholar
  31. [31]
    R. Lipsett, C. Schaefer, and C. Ussery, VHDL: Hardware Description and Design. Dordrecht, The Netherlands: Kluwer Academic Publishers, 1989.CrossRefGoogle Scholar
  32. [32]
    G. Mealy, “A method for synthesizing sequential circuits,” Bell Systems Technical Journal, vol. 34, pp. 1045–1079, Sept. 1955.MathSciNetGoogle Scholar
  33. [33]
    S. Muroga, Y. Kambayashi, H. C. Lai, and J. N. Culliney, “The transduction method - design of logic networks based on permissible functions,” IEEE Transactions on Computers, vol. C-38, pp. 1404–1424, Oct. 1989.MathSciNetCrossRefGoogle Scholar
  34. [34]
    M. Paull and S. Unger, “Minimizing the number of states in incompletely specified sequential switching functions,” IRE Transactions on Electronic Computers, vol. EC-8, pp. 356–367, Sept. 1959.CrossRefGoogle Scholar
  35. [35]
    C. Pixley, V. Singhal, A. Aziz, and R. K. Brayton, “Multi-level synthesis for safe replaceability,” in Proceedings of the IEEE International Conference on Computer-Aided Design, (San Jose, CA), pp. 442–449, IEEE, November 1994.Google Scholar
  36. [36]
    J.-K. Rho, G. Hachtel, and F. Somenzi, “Don’t care sequences and the optimization of interacting finite state machines,” in Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 418–421, Nov. 1991.Google Scholar
  37. [37]
    J.-K. Rho, G. Hachtel, F. Somenzi, and R. Jacoby, “Exact and heuristic algorithms for the minimization of incompletely specified state machines,” IEEE Transactions on Computer-Aided Design, vol. 13, pp. 167–177, Feb. 1994.CrossRefGoogle Scholar
  38. [38]
    J. P. Roth, “Diagnosis of automata failures: A calculus and a method,” IBM Journal of Research and Development, vol. 10, pp. 278–291, 1966.CrossRefMATHGoogle Scholar
  39. [39]
    H. Savoj and R. Brayton, “The use of observability and external don’t cares for the simplification of multi-level networks,” in Proceedings of the 27th Design Automation Conference, pp. 297–301, June 1990.Google Scholar
  40. [40]
    E. M. Sentovich, K. J. Singh, C. Moon, H. Savoj, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, “Sequential circuit design using synthesis and optimization,” in Proceedings of the International Conference on Computer Design, pp. 328–333, October 1992.Google Scholar
  41. [41]
    E. Sentovich, V. Singhal, and R. Brayton, “Multiple Boolean relations,” in Proceedings of the International Workshop on Logic Synthesis, (Tahoe City, California), May 1993.Google Scholar
  42. [42]
    J. P. M. Silva and K. A. Sakallah, “Grasp - a new search algorithm for satisfiability,” in Proceedings of the IEEE International Conference on Computer-Aided Design, (Santa Clara, CA), pp. 220–227, IEEE, November 1996.Google Scholar
  43. [43]
    V. Singhal, Y. Watanabe, and R. Brayton, “Heuristic minimization of synchronous relations,” in Proceedings of the International Conferenceon Computer Design, pp. 428–433, Oct. 1993.Google Scholar
  44. [44]
    S. Sinha and R. Brayton, “Implementation and use of SPFDs in optimizing Boolean networks,” in Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 103–110, Nov. 1998.Google Scholar
  45. [45]
    L. Stok, D. Kung, D. Brand, A. Drumm, A. Sullivan, L. Reddy, N. Hieter, D. Geiger, H. Chao, and R Osier, “Booledozer: Logic synthesis for ASICs,” IBM Journal of Research and Development, vol. 40, pp. 407–430, July 1996.CrossRefGoogle Scholar
  46. [46]
    P. Tafertshofer, A. Ganz, and K. Antreich, “Igraine — an implication graph based engine for fast implication, justification and propagation,” IEEE Transactions on Computer-Aided Design, vol. CAD-19, pp. 907–927, August 2000.CrossRefGoogle Scholar
  47. [47]
    D. E. Thomas and P. Moorby, The Verilog Hardware Description Language. The Netherlands: Kluwer Academic Publishers, 1991.CrossRefGoogle Scholar
  48. [48]
    H. Wang and R. Brayton, “Permissible observability relations in interacting finite state machines,” in Proceedings of the International Workshop on Logic Synthesis, (Tahoe City, California), May 1993.Google Scholar
  49. [49]
    H.-Y. Wang and R. Brayton, “Input don’t care sequences in FSM networks,” in Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 321–328, Nov. 1993.Google Scholar
  50. [50]
    Y. Watanabe and R. Brayton, “Heuristic minimization of multiple-valued relations,” in Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 126–129, Nov. 1991.Google Scholar
  51. [51]
    Y. Watanabe and R. Brayton, “The maximum set of permissible behaviors for FSM networks,” in Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 316–320, Nov. 1993.Google Scholar
  52. [52]
    Y. Watanabe and R. Brayton, “State minimization of pseudo non-deterministic FSMs,” in Proceedings of the European Conference on Design Automation, 1994.Google Scholar
  53. [53]
    S. Yamashita, H. Sawada, and A. Nagoya, “A new method to express functional permissibilities for lut-based fpgas and its applications,” in Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 254–261, Nov. 1996.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media New York 2002

Authors and Affiliations

  • Ellen Sentovich
  • Daniel Brand

There are no affiliations available

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