Morphological Investigations of Low-k Polymer/Diffusion Barrier Interfaces for IC Metallization

Abstract

Until recently, the performance of complementary metal-oxide semiconductor (CMOS) integrated circuits (ICs) has been driven by front-end device (i.e. transistor) size scaling. However, as the IC critical dimension (CD) shrinks, interconnect latency has emerged as a primary performance driver. This has hastened the integration of copper and low-k dielectrics in back-end processing to reduce the effective signal propagation delays associated with on-chip interconnects. With current dielectric materials, the use of Cu in CMOS processing requires a barrier layer between the Cu and the dielectric to prevent thermal and bias-induced Cu-ion diffusion. In some cases (such as low-k polymers) this barrier also serves to prevent oxidation of the Cu line due to diffusion of water vapor through the dielectric. To preserve the cross-sectional ‘real estate’ of the Cu interconnect, the International Roadmap for Semiconductors calls for barrier-layer thickness less than 10 nm prior to the 100 nm device node.¹ Consequently, new material sets are being investigated to provide chemically, electrically, and thermally stable barriers against Cu diffusion that maintain satisfactory performance at such low thickness.