Abstract
The architectural construction of an electronic system from individual integrated circuits (ICs) and other components is dependent upon effective interconnection substrates and means of connecting to them (chip-to-module connections). Traditionally, general packaging, assembly, and chip-to-module connections were available and applied to devices. A close interaction between IC design and substrate technology was not required. Early ICs used transistor-transistor logic which had long internal delays (e.g. 15 ns) making the interconnect and module delays irrelevant. The number of input and output (I/O) connections was small, the DC power was minimal, and packaging density of silicon on boards was sparse. This made cost, reliability, and yield the focus of the chip-to-module connection technology.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
International Technology Roadmap for Semiconductors (ITRS), SIA/Sematech International (http://public.itrs.net/)
P. Garrou, “Wafer Level Chip Scale Packaging”, Semi Chip Scale International’99, page D–l (1999).
“Fundamentals of Microsystems Packaging”, R. Tummala Ed., Mc-Graw Hill, 2001.
H. I. Rosten, and R. Viswanath, “Thermal Modeling of the Pentium Processor Package”, in Proc. of ECTC, pp. 421, 1994.
Printed Circuit Board Materials Handbook, Martin W. Jawitz, McGraw-Hill (1997).
Y. Sato, K. Sasaoka, K. Shibayama, H. Hamano, and Y. Fukuoka, “A New PCB Utilizing Buried Interconnection Technology (B2it)”, in Proc. 7th Printed Circuit World Convention, pp. 19–1 to 6, May 1998.
H. Iwaki, Y Taguchi, T. Shiraishi, Y Bessho, and K. Eda, “High Frequency Electrical Characterization of a High Wiring Density Organic Substrate “ALIVH” and a Stud Bump Bonding SBB”, in Proc. IEEE International Symposium on Microelectronics, pp. 341, 1998.
R. Maniwa, “Finer Micro-via PWB by Laser and Additive Process”, in Proc. IEEE International Symposium on Microelectronics, pp. 413, 1998.
R. Enomoto, M. Asai, and N. Hirose, “High Density MLB using Additive and Build- up Process”, in Proc. IEEE International Symposium on Microelectronics, pp. 399, 1998.
A. Naeemi, P. Zarkesh-Ha, C. S. Patel, and J. D. Meindl, “Performance Improvement Using On-Board Wires for On-Chip Interconnects”, in Proc. IEEE 9th Topical meeting on Electrical Performance of Electronic Packaging, pp. 325–328, Oct. 2000.
M. S. Bakir, H. A. Reed, P. A. Kohl, K. P. Martin, and J. D. Meindl, “Sea of Leads ultra high-density compliant wafer level packaging technology,” in Proc. 52nd Electronics and Components Technology Conf., (San Diego, CA), May 2002.
C. S. Patel, K. Martin, J. D. Meindl, P. A. Kohl, C. Powers, and M. Realff, “Low cost high density compliant wafer level package,” in Proc. International Conf. on High-Density Interconnect and Systems Packaging, (Denver, CO), pp. 261–268, April 26–28, 2000.
M. S. Bakir, H. A. Reed, A. V. Mule, P. A. Kohl, K. P. Martin, and J. D. Meindl, “Sea of Leads characterization and design for compatibility for board level optical waveguide interconnection,” in Proc. IEEE Custom Integrated Circuits Conference, (Orlando, FL), May 2002.
Kohl, P. A., Bhusari, D. M., Wedlake, M., Case, C, Lee, B. C, Gutmann, R. J., and Shick, R., “Air Gaps in 0.3 µm Electrical Interconnections”, Electron Device Letters, vol. 21, pp. 557–560, 2000.
H.A. Reed, C.E. White, V. Rao, S.A. Allen, C.L. Henderson, and P.A. Kohl, “Fabrication of Microchannels Using Polycarbonates as Sacrificial Materials”, Journal of Micromechanics and Microengineering, vol. 11, pp. 733–737, 2001.
D. Bhusari, H. Reed, M. Wedlake, A. Padovani, S.A. Bidstrup-Allen, P.A. Kohl, “Fabrication of Air-Channel Structures for Microfluidic, Microelectro-mechanical and Microelectronic Applications”, Journal of Microelectromechanical Systems, vol. 10, pp. 400–409, 2001.
Z. Feng, W. Zhang, S. Bingzhi, K. C. Gupta, and Y. C. Lee, “RF and mechanical characterization of flip-chip interconnects in CPW circuits with underfill,” IEEE Trans. On Microwave Theory and Techniques, Vol. 46, pp. 2269–2275, 1998.
H. Kusamitsu, Y. Morishta, M. Ito, and K. Ohata, “The flip-chip bump interconnection for millimeter-wave GaAs MMIC,” IEEE Trans. Electron. Packaging Manufact., vol. 22, pp. 23–28, Jan. 1999.
P. J. Restle, T. G. Mcnamara, D. A. Webber, P. J. Camporese, K. F. Eng, K. A. Jenkins, D. H. Allen, M. J. Rohn, M. P. Quaranta, D. W. Boerstler, C. J. Alpert, C. A. Carter, R. N. Bailey, J. G. Petrovick, B. L. Krauter, and B. D. McCredie, “A clock distribution network for microprocessors,” IEEE J. Solid State Circuits, vol. 36, pp. 792– 799, May 2001.
A. Jain, S. Rogojevic, S. Ponoth, N. Agarwal, I. Matthew, W. N. Gill, P. Persans, M. Tomozawa, J. L. Plawsky, and E. Simonyi, “Porous silica materials as low-k dielectrics for electronic and optical interconnects,” Thin Solid Films, vol. 398–399, pp. 513–522, 2001.
A. V. Mule, S. Schultz, E. N. Glytsis, T. K. Gay lord, and J. D. Meindl, “Input coupling and guided-wave distribution scheme for board-level intra-chip optical clock distribution network using volume grating coupler technology,” in Proc. IEEE International Interconnect Technology Conference, (San Francisco, CA), pp. 128–130, June 2001.
L. Ma, Q. Zhu, T. Hantschel, D. K. Fork, and S. K. Sitaraman, “J-Springs-Innovative Compliant Interconnects for Next-Generation Packaging”, in Proceedings ECTC, 2002.
L. Ma, Q. Zhu, W. K. Sitaraman, C. Chua, and D. K. Fork, “Compliant Cantilevered Spring Interconnects for Flip-chip Packaging”, in Proced-ings ECTC, 2002.
Q. Zhu, L. Ma, and S. K. Sitaraman, “design Optimization of One Turn Helix”, in Proc. Itherm, 2002.
Q. Zhu, L. Ma, and S. K. Sitaraman, “Mechanical and Preliminary Electrical Design of a Novel Complinat One-turn Helix Interconnect”, in Proc. InterPACK-01, 2001.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2003 Springer Science+Business Media New York
About this chapter
Cite this chapter
Kohl, P. (2003). Chip-to-Module Interconnections. In: Davis, J., Meindl, J.D. (eds) Interconnect Technology and Design for Gigascale Integration. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-0461-0_8
Download citation
DOI: https://doi.org/10.1007/978-1-4615-0461-0_8
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-5088-0
Online ISBN: 978-1-4615-0461-0
eBook Packages: Springer Book Archive