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Scaling Trends of On-Chip Power Distribution Noise

  • Andrey V. Mezhiba
  • Eby G. Friedman

Abstract

A scaling analysis of the voltage drop across the on-chip power distribution networks is performed in this chapter. The design of power distribution networks in high performance integrated circuits has become significantly more challenging with recent advances in process technology. Insuring adequate signal integrity of the power supply has become a primary design issue in high performance, high complexity digital integrated circuits. A significant fraction of the on-chip resources is dedicated to achieve this objective.

Keywords

Power Distribution Transient Current Technology Node Resistive Noise Minimum Feature Size 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 2004

Authors and Affiliations

  • Andrey V. Mezhiba
    • 1
  • Eby G. Friedman
    • 1
  1. 1.Department of Electrical and Computer EngineeringUniversity of RochesterRochesterUSA

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