Scaling Trends of On-Chip Power Distribution Noise
A scaling analysis of the voltage drop across the on-chip power distribution networks is performed in this chapter. The design of power distribution networks in high performance integrated circuits has become significantly more challenging with recent advances in process technology. Insuring adequate signal integrity of the power supply has become a primary design issue in high performance, high complexity digital integrated circuits. A significant fraction of the on-chip resources is dedicated to achieve this objective.
KeywordsPower Distribution Transient Current Technology Node Resistive Noise Minimum Feature Size
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