Abstract
Advances in silicon technology have fueled much of the growth in SoC performance and density. Yet these technology advances have not come easily: each new technology generation brings with it a new set of technology related design considerations and challenges. This chapter outlines the major technology issues facing current and future SoC designers. These challenges are divided into issues that influence design, those that influence manufacture and those that relate to affordability. The design issue section outlines problems relating to performance scaling, power management, signal integrity, parametric variability and reliability. The manufacturability section describes issues relating to manufacturing yield and lithography challenges. Finally, the affordability section covers issues relating to rising engineering costs and technology trends. Each topic begins with a summary of the principal issues and trends, followed by a discussion of the associated SoC impact and mitigation strategies.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Paul S. Zuchowski et. al., “A Hybrid ASIC and FPGA Architecture”, ICCAD 2002, November, 2002, pp. 187–194.
S. Crowder, R. Hannon, H. Ho, D. Sinitsky, S. Wu, K. Winstel, B. Khan, S.R. Stiffler, and S.S. Iyer, “Integration of Trench DRAM into a High Performance 0.18um Logic Technology with Copper BEOL”, International Electron Devices Meeting, 1998, pp. 1017–1020.
http.://www-3.ibm.com/chips/products/asics/products/low-k.html/.
K. Chuang and R. Puri, “SOI Digital CMOS VLSI — A Design Perspective”, 36th. Design Automation Conference, June, 1999.
URL: http://news.com.com/2100-1001-268083.html/.
J. Kedzierski, et. al. “Metal-Gate FinFET and Fully-Depleted SOI Devices Using Total Gate Silicidation”, IEDM 2002.
Ron Ho, Ken Mai, Herna Kapadia and Mark Horowitz, “Interconnect scaling implications for CAD”, ICCAD 1999, pp. 425–429.
URL: http://www.chips.ibm.com/techlib: 128bitPIbBus.pdf/.
Girish Varatkar and Radu Marculescu, “Traffic Analysis for On-Chip Network Design of Multimedia Applications”, 39th Design Automation Conference, June, 2002.
M. Igarashi, T. Mitsuhashi, A. Lee, et. al., “A Diagonal-Interconnect Architecture and its Application to RISC Core Design”, ISSCC 2002.
URL: http://www.xinitiative/.org/wt/home_flash.php/.
E.J. Nowack, “Maintaining the Benefits of CMOS Scaling when Scaling Bogs Down”, IBM Journal of Research and Development, Number 2/3, March/May 2002.
URL: http://public.itrs.net/Files/2002Update/2002Update.pdf/.
International Technology Roadmap for Semiconductors (ITRS), 2002 edition, System Drivers Chapter.
Wolfgang Nebel, Power Estimation at the Logic Level, Kluwer Academic Publishers, Dordrecht, Netherlands.
“IBM lowers power 10X on PowerPC 405”, EETimes, October 15, 2001. URL: http://www.eedesign.com/isd/OEG20011011S0076/.
B.R. Stanisic, N.K. Verghese, R.A. Rutenbar, L.R. Carley, and D.J. Allstot, “Addressing Substrate Coupling in Mixed-Mode ICs: Simulation and Power Distribution Synthesis”, IEEE Journal of Solid-State Circuits, volume 29, March, 1994, pp. 226–237.
John Darringer et. al., “EDA in IBM: Past, Present and Future”, IEEE Transactions on CAD, Volume 19, number 12, December, 2000.
D.E. Lackey, P.S. Zuchowski, T.R. Bednar, D.W. Stout, S.W. Gould, and J.M. Cohn, “Managing Power and Performance for System-on-Chip Designs using Voltage Islands”, International Conference on Computer-Aided Design (ICCAD), San Jose, California, November, 2002.
S.R. Nassif and J.N. Kozhaya, “Fast Power Grid Simulation”, 37th. Design Automation Conference, Los Angeles, June 2000, pp. 156–161.
K. Bernstein, “Design, process and environmental contributors to CMOS Delay variation”, SSCTC Workshop, 2003.
S. Nassif, “Modeling and Forecasting of Manufacturing Variations”, Asia-Pacific DAC, 2001.
C. Visvesvariah, “Death, Taxes and Falling Chips”, Proceedings of TAU 2002.
Y. Mitani, et. al., “NBTI Mechanism in Ultra-thin Gate Dielectrics — Nitrogen-Oriented Mechanism in SION”, IEDM 2002.
US patents: US 6,305,004: Method for improving wiring related yield and capacitance properties of integrated circuits by maze-routing, Gustavo Tellez et. al.; US 6,189,132: Design rule correction system and method, F. Heng et. al.
M. Lavin and L. Leibman, “CAD Computation for Manufacturability: Can We Save VLSI Technology from Itself?”, ICCAD 2002.
URL: http://www.gigascale.org/pubs/reports/reports/GSRClQ02Web.htm/.
M. Hatamian, et. al. “Design Considerations for Gigabit Ethernet 1000Base-T Twisted Pair Transceivers”, Custom Integrated Circuits Conference (CICC) 1998.
H.B. Pogge, “The Next Chip Challenge: Effective Methods for Viable Mixed Technology SoCs”, Design Automation Conference, 2002.
J. Dufresne, S. Ouimet and T.R. Homa, “Hybrid Assembly Technology for Flip-Chip-on-Chip (FCOC) Using PBGA Laminate Assembly”, ECTC’00: Electronic Components and Technology Conference, 2000.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2003 Springer Science+Business Media New York
About this chapter
Cite this chapter
Cohn, J.M. (2003). Technology Challenges for SOC Design. In: Martin, G., Chang, H. (eds) Winning the SoC Revolution. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-0369-9_11
Download citation
DOI: https://doi.org/10.1007/978-1-4615-0369-9_11
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-5042-2
Online ISBN: 978-1-4615-0369-9
eBook Packages: Springer Book Archive