Aspect partitioning for Hardware Verification Reuse

Abstract

Technology advances strongly impact integrated circuits (IC) complexity. Current IC design methods have difficulties to handle this growth. In particular, hardware verification has become the main bottleneck of any major digital design effort. It is thus necessary to develop efficient methodologies for designing verification environments. To deal with this complexity, hardware verification languages (HVL), such as e, allow reducing the verification effort and contribute to raise the level of abstraction at which test benches are described. In addition, aspect-oriented programming (AOP) is an emerging technique, which promotes a better separation of concerns and improves reusability. We propose a partitioning method based on e, which uses AOP to facilitate verification program development, and we apply our method to a concrete example; verification of a subset of a SOC protocol converter platform.