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An Approach to Flexible Multi-Level Network Design

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Abstract

The paper is focused on integrating the flexibility in the design of logic networks. We achieve the flexibility by several ways: evolving the design and applying the decomposition technique. To perform the circuit evolution, we use one of more powerful techniques borrowed from information theory and decision making, to evaluate the design. This technique can be used along with any multi-level networks design optimisation strategy over a fixed library of cells. As an example, we use the evolutionary network synthesis and our previously introduced concept of a target design style. Also, in order to alleviate the problem of large-size network search space, we use the partition of the space by the state-of-the-art decomposition technique.

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References

  1. T.Aoki, N.Homma and T. Higuchi. Evolutionary design of arithmetic circuit. IEICE Transactions on Fundamentals E-82-A(5):798–806,1999.

    Google Scholar 

  2. J.A. Brzozowski and T. Luba Decomposition of Boolean Function specified by Cubes, Part l: Theory of serial decomposition using blankets. Part 2 (with M.Nowicka): Practical Results. n research Report CS-97-01, Dept of CompSci., University of Waterloo, Canada, 1997, Revised in October 1998.

    Google Scholar 

  3. R.Drechsler and W.Gunther. Exact circuit synthesis. In International Owrkshop on Logic Synthesis, Lake Tahoe, 1998

    Google Scholar 

  4. D.Quaglirella et al. (Eds) Genetic Algorithm and Evolution Strategies in Engineering and Computer Science. Recent Advances and Industrial Aplications. John Wiley and Sons Ltd. 1998.

    Google Scholar 

  5. M.Siper et al (Eds) Evolvable Systems: From Biology to hardware lecture notes in compuer science, vol 1478, Springer 1998.

    Google Scholar 

  6. L. J_ozwiak and A. Chojnacki. Functional decomposition based on information relationship measures extremely effective for symmetric functions. In Proc. EUROMICRoConf., pages 150.159, 1999.

    Google Scholar 

  7. T. €uba, C. Moraga, S. Yanushkevich, M. Opoka, and V. Shmerko. Evolutionary multilevel network synthesisin given design style. In Proc. IEEE Int. Symposium on Multiple-Valued Logic, 2000.

    Google Scholar 

  8. T. €uba, C. Moraga, S. Yanushkevich, V. Shmerko, and J. Kolodziejczyk. Application of Design Style in Evolu-tionary Multi-Level Networks Synthesis, In Proc. IEEEInt. Symposium on Digital System Design (DSD′2000), Netherlands, pages 156.163, 2000.

    Google Scholar 

  9. V. Cheushev, S. Yanushkevich, C. Moraga, V. Shmerko, and J. Kolodziejczyk. Remarks on circuit verification through the evolutionary circuit design, In Proc. IEEE31-th Int. Symp. on Multiple-Valued Logic, pages 201.206, 2001.

    Google Scholar 

  10. V. Cheushev, S. Yanushkevich, C. Moraga, V. Shmerko. Research Report, Flexibility in Logic Design. An Approach Based on Information Theory Methods, Forschungsbericht 741, University of Dortmund, Germany.

    Google Scholar 

  11. C. Moraga and W. Wang. Evolutionary methods in the design of quaternary digital circuits. In Proc. IEEE 28thInt. Symposium on Multiple-Valued Logic, pages 89.94, 1998.

    Google Scholar 

  12. Proc. NASA/DoD Workshop on Evolvable Hardware, Pasadena, California. 1999.

    Google Scholar 

  13. SIS Release 1.2. In UC Berkeley Soft. Distr., July, 1994.

    Google Scholar 

  14. V. P. Shmerko, D. V. Popel, R. S. Stankovic, V. A. Cheushev, and S. N. Yanushkevich. Information theoretical approach to minimization of AND/EXOR expressions of switching functions. In Proc. IEEE Int. Conf. on Telecommunications in Modern Satellite, Cable and Broadcasting Services, pages 444.451, 1999.

    Google Scholar 

  15. K. S. Tang, K.F. Man, and S. Kwong. Parallel genetic algorithms: Implemental hardware solutions. Circuit and Systems, 10(2):3,8.11, 1999.

    Google Scholar 

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Cheushev, V. et al. (2003). An Approach to Flexible Multi-Level Network Design. In: Badawy, W., Jullien, G. (eds) System-on-Chip for Real-Time Applications. The Kluwer International Series in Engineering and Computer Science, vol 711. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-0351-4_20

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  • DOI: https://doi.org/10.1007/978-1-4615-0351-4_20

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4613-5034-7

  • Online ISBN: 978-1-4615-0351-4

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