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Novel Test Methodologies for SoC/IP Design

Implementation and Comparison
  • L. Hong
  • M. Nahvi
  • R. Fung
  • A. Ivanov
  • R. Saleh
Part of the The Kluwer International Series in Engineering and Computer Science book series (SECS, volume 711)

Abstract

This paper addresses testing issues associated with System-on-Chip (SoC) designs. A network-processing engine SoC was constructed using reusable Intellectual Property (IP) and a test harness based on the emerging IEEE P1500 standard. Three different test access mechanisms (TAMs) are compared on this platform — a serial threading approach analogous to the IEEE1149.1 standard, a test-rail approach, and a packet-switching test network (NIMA). The NIMA architecture is the most effective when there is a limited number of I/O pins and could potentially become the fastest architecture when it is allowed to operate at higher clock speed than the core DFT. However, the test rail approach is the most effective of the three TAMs if the test width is not restricted or if the area overhead is critical.

Keywords

Test Time Area Overhead Test Width Network Processor Design Automation Conference 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 2003

Authors and Affiliations

  • L. Hong
    • 1
  • M. Nahvi
    • 1
  • R. Fung
    • 1
  • A. Ivanov
    • 1
  • R. Saleh
    • 1
  1. 1.Dept. of Electrical and Computer EngineeringUniversity of British ColumbiaVancouverCanada

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