Novel Test Methodologies for SoC/IP Design
This paper addresses testing issues associated with System-on-Chip (SoC) designs. A network-processing engine SoC was constructed using reusable Intellectual Property (IP) and a test harness based on the emerging IEEE P1500 standard. Three different test access mechanisms (TAMs) are compared on this platform — a serial threading approach analogous to the IEEE1149.1 standard, a test-rail approach, and a packet-switching test network (NIMA). The NIMA architecture is the most effective when there is a limited number of I/O pins and could potentially become the fastest architecture when it is allowed to operate at higher clock speed than the core DFT. However, the test rail approach is the most effective of the three TAMs if the test width is not restricted or if the area overhead is critical.
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