Abstract
This paper addresses testing issues associated with System-on-Chip (SoC) designs. A network-processing engine SoC was constructed using reusable Intellectual Property (IP) and a test harness based on the emerging IEEE P1500 standard. Three different test access mechanisms (TAMs) are compared on this platform — a serial threading approach analogous to the IEEE1149.1 standard, a test-rail approach, and a packet-switching test network (NIMA). The NIMA architecture is the most effective when there is a limited number of I/O pins and could potentially become the fastest architecture when it is allowed to operate at higher clock speed than the core DFT. However, the test rail approach is the most effective of the three TAMs if the test width is not restricted or if the area overhead is critical.
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References
E.J. Marinissen, Y. Zorian, “Challenges in Testing Core-Based System ICs”, IEEE Communication Magazine, June 1999, pp. 104–109.
Y. Zorian, E.J. Marinissen, S. Dey, “Testing Embedded-Core Based System Chips”, Proc. IEEE ITC, 1998, pp. 130–143.
I. Ghosh, N.K. Jha, S. Dey, “A Low Overhead Design for Testability & Test Generation Technique for Core-Based Systems”, Proc. IEEE ITC, 1999, pp. 50–59.
L. Whestsel, “An IEEE 1149.1 Based Test Access Architecture for ICs with Embedded Cores”, Proc. IEEE ITC, 1997, pp. 69–78.
Debashis Bhattacharya, “Hierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit”, Proc. VLSI Test Symposium, 1998, pp. 8–14.
A. Benso et al, “HD2BIST: Architectural Framework for BIST Scheduling, Data Patterns delivering & Diagnosis in SoCs”, Proc. IEEE ITC, 2000, pp. 892–901.
E.J. Marinissen, R. Arendsen, G. Bos et al, “A structured & Scalable Mechanism for Test Access to Embedded Reusable Cores”, Proc. IEEE ITC, 1998, pp. 284–293.
Mohsen Nahvi, Andre Ivanov, “A Packet Switching Communication-Based Test Access Mechanism for System Chips”, Proc. IEEE European Test Workshop, 2001, pp. 81–86.
William J. Dally, Brian Towles, “Route Packets, Not Wires: On-Chip Interconnection Networks”, Design Automation Conference (DAC), 2001
Stephen J. Sheafor, “Network Processors: Ushering in a New Era of Performance and Flexibility”, http://www.sitera.com.
M. Keating, P. Bricaud, Reuse Methodology Manual, 2nd Edition, Kluwer Academic Publishers, 1999.
“AMBA Specification Rev 2.0”, http://www.ann.com .
Drew Wingard, “MicroNetwork-Based Integration for SOCs”, Design Automation Conference (DAC), 2001
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© 2003 Springer Science+Business Media New York
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Hong, L., Nahvi, M., Fung, R., Ivanov, A., Saleh, R. (2003). Novel Test Methodologies for SoC/IP Design. In: Badawy, W., Jullien, G. (eds) System-on-Chip for Real-Time Applications. The Kluwer International Series in Engineering and Computer Science, vol 711. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-0351-4_12
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DOI: https://doi.org/10.1007/978-1-4615-0351-4_12
Publisher Name: Springer, Boston, MA
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