Abstract
This paper presents a formal approach to the worst-case design of Integrated Circuits, yielding realistic estimates of variations in device performances. The worst-case analysis is performed in terms of statistically independent process disturbances and employs the statistical process simulator, FABRICS II.
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References
Wojciech Maly and Andrzej J. Strojwas. “Statistical Simulation of the IC Manufacturing Process”, IEEE Trans. CAD, Vol. 1, March 1982.
Sani R. Nassif and Anrzej J. Strojwas and Stepehn. W. Director. “FABRICS-II: A Statistical Simulator of the IC Fabrication Process”, Proceedings of International Conference on Circuits and Computers, September 1982.
Andrzej. J. Strojwas. “A Pattern Recognition Based System for IC Failure Analysis”, PhD Thesis, Carnegie-Mellon University, 1982.
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© 2003 Springer Science+Business Media New York
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Strojwas, A.J., Nassif, S.R., Director, S.W. (2003). A Methodology for Worst Case Design of Integrated Circuits. In: Kuehlmann, A. (eds) The Best of ICCAD. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-0292-0_44
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DOI: https://doi.org/10.1007/978-1-4615-0292-0_44
Publisher Name: Springer, Boston, MA
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