Embedded Memory Design Validation and Design For Test
Design verification and design for test go hand-in-hand because of the close interactions between the two. There is a tradeoff between the overhead of making a design correctly by construction or through extensive verification for logic and circuit in terms of power, area, cost, and speed. The end goal of any design is to have a competitive product that meets market goals in terms of performance, power, cost, and time to market. Chapter 4 discussed in detail the impact of process variation on circuit performance and how it affects product yield; design verification and design testing are two important steps in design cycle that aim to get a functional design with high yield. The difference between verification and testing (validation) is that verification is done pre-fabrication, using different levels of design abstraction, while silicon validation is post-fabrication. For example, the first level of verification uses a verilog view of the memory and focuses on functionality and logic correctness using CAD tools, while gate level verification uses gate level view with some abstraction for memory cell to verify timing constraints in addition to basic functionality. Chapter 7 discussed verification part in details and this chapter is focusing on design for test and silicon validation.
- 1.Wilkes, M. The memory gap and the future of high performance memories, ACM Computer Architecture News, vol. 29, March 2001, pp. 2-7.Google Scholar
- 64.Mohammad, B; Seok, G.; Kim, H. Verification of gate level model for custom design in scan mode, IEEE Microprocessor Test and Verification Conf., December 2007.Google Scholar