Power and Yield for SRAM Memory

  • Baker Mohammad
Chapter
Part of the Analog Circuits and Signal Processing book series (ACSP, volume 116)

Abstract

As noted in the previous chapter, supply voltage, cell ratio, and threshold voltage of the devices are the factors that determine whether a cell is robust and stable. In addition to these factors, controlling variability through process technology further reduces the device parameter shift. The SRAM cell stability and its effect on both yield and power have been addressed through several techniques, and they are as follows:

References

  1. 33.
    Yamaoka, M et al. 90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique, IEEE J. Solid-State Circuits, volume 42, March 2006, pp. 705–711.CrossRefGoogle Scholar
  2. 34.
    Pilo, H. et al. An SRAM Design in 65nm technology node featuring read and write-assist circuits to expand operating voltage, IEEE J. Solid-State Circuits, volume 42, April 2007, pp. 813–819.CrossRefGoogle Scholar
  3. 38.
    K.-L. C. K.-L. Cheng, C. C. Wu, Y. P. Wang, D. W. Lin, C. M. Chu, Y. Y. Tarng, S. Y. Lu, S. J. Yang, M. H. Hsieh, C. M. Liu, S. P. Fu, J. H. Chen, C. T. Lin, W. Y. Lien, H. Y. Huang, P. W. Wang, H. H. Lin, D. Y. Lee, M. J. Huang, C. F. Nieh, L. T. Lin, C. C. Chen, W. Chang, Y. H. Chiu, M. Y. Wang, C. H. Yeh, F. C. Chen, Y. H. Chang, S. C. Wang, H. C. Hsieh, M. D. Lei, K. Goto, H. J. Tao, M. Cao, H. C. Tuan, C. H. Diaz, Y. J. Mii, and C. M. Wu, A highly scaled, high performance 45 nm bulk logic CMOS technology with 0.242 amp;#x003BC;m2 SRAM cell. IEEE, 2007, pp. 243–246.Google Scholar
  4. 39.
    Kuhn, K. Reducing variation in advanced logic technologies: Approaches to process and design for manufacturability of nano scale CMOS, Proc. IEDM, December 2007, pp. 471–474.Google Scholar
  5. 40.
    Wang, Y. et al. A 1.1 GHz 12 µA/Mb-Leakage SRAM in 65 nm ultra-low-power CMOS technology with integrated leakage reduction for mobile applications, Proc. ISSCC; January 2008; pp. 172–179.Google Scholar
  6. 42.
    L. Chang, D. M. Fried, J. Hergenrother, J. W. Sleight, R. H. Dennard, R. K. Montoye, L. Sekaric, S. J. McNab, A. W. Topol, C. D. Adams, K. W. Guarini, and W. Haensch, Stable SRAM cell design for the 32 nm node and beyond. IEEE, 2005, pp. 128–129.Google Scholar
  7. 44.
    K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N. Vallepalli, Y. Wang, B. Zheng, and M. Bohr, “SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction,” IEEE J. Solid State Circuits, vol. 40, no. 4, pp. 895–901, 2005.Google Scholar
  8. 45.
    Royannez, P;Mair H., and Dahan F. 90nm low leakage SOC design techniques for wireless applications, IEEE ISSCC Multimedia, 2005; pp. 138–141.Google Scholar
  9. 46.
    E. Karl, Y. Wang, Y.-G. Ng, Z. Guo, F. Hamzaoglu, U. Bhattacharya, K. Zhang, K. Mistry, and M. Bohr, “A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry,” in 2012 IEEE International SolidState Circuits Conference, 2012, pp. 230–232.Google Scholar
  10. 51.
    K. Nii, Yabuuchi, M.; Tsukamoto, Y.; Ohbayashi, S.; Imaoka, S.; Makino, H.; Yamagami, Y.; Ishikura, S.; Terano, T.; Oashi, T.; Hashimoto, K.; Sebe, A.; Okazaki, S.; Satomi, K.; Akamatsu, H.; Shinohara, H. A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations, IEEE J. Solid-State Circuits IEEE, April 2007, pp. 820–829.Google Scholar
  11. 52.
    Tran, C.Q. Low-power High-speed Level Shifter Design for Block-level Dynamic Voltage Scaling Environment, IEEE International Conf. on Integrated Circuit and Technology, 2005, pp. 229–232.Google Scholar
  12. 53.
    Zhang, K.; Bhattacharya, U.; Zhanping Chen; Hamzaoglu, F.; Murray, D.; Vallepalli, N.; Yih Wang; Bo Zheng; Bohr, M. A 3-GHz 70-Mb SRAM in 65-nm CMOS Technology With Integrated Column-Based Dynamic Power Supply, IEEE J. Solid-State Circuits, volume 41, April 2006, pp. 146–152.Google Scholar
  13. 55.
    Mukhopadhyay, S; Kim, K.; Mahmoodi, H.; Roy, K. Design of a Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS, IEEE J. Solid-State Circuits, volume 42, June 2007, pp. 1370–1376. CrossRefGoogle Scholar
  14. 69.
    H. Melzner and A. Olbrich, Maximization of Good Chips Per Wafer by Optimization of Memory Redundancy, vol. 20, no. 2. 2007, pp. 68–76.Google Scholar
  15. 70.
    J. P. Bickford, R. Rosner, E. Hedberg, J. W. Yoder, and T. S. Barnett, SRAM Redundancy—Silicon Area versus Number of Repairs Trade-off. IEEE, 2008, pp. 387–392.Google Scholar

Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  • Baker Mohammad
    • 1
  1. 1.Khalifa University of Science, Technology and ResearchAbu DhabiUnited Arab Emirates

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