Cache Architecture and Main Blocks

  • Baker Mohammad
Chapter
Part of the Analog Circuits and Signal Processing book series (ACSP, volume 116)

Abstract

Embedded memory architecture is important as it is the first step in designing the memory subsystem and in deciding how the cache fits in the big picture. Since TCM is a simpler version of cache, in this book we will concentrate on cache design. Cache architecture is normally led by the micro architecture team with strong input from circuit design and process technology. Circuit design input provides area, access time, and power for a given cache size. Process technology team provides leakage estimation per memory cell type, expected yield, and soft error rate per cell type. The key decisions at the end of this effort is a spec outlining the cache hierarchy and size for each cache level, associativity, replacement policy, cache line, and cache blocks access (serial versus parallel) [6, 7, 26]. The process of reaching a decision is much like a negotiation process between the three main disciplines and as each one is an expert in his own domain the knowledge of the other domain is valuable in reaching optimum solution. For example, if the architecture experts understand some of the limitations on the circuit side like minimum voltage requirements, cell size versus performance versus leakage then he/she can propose innovative solutions on the architectural level to deal with retention, voltage island, etc. In the same way, circuit design knowledge of architecture and how the address and data are generated and consumed will help optimize the overall timing path.

References

  1. 6.
    Hennessy, J. and Patterson, D. Computer Organization & Design, 3rd ed., Morgan Kaufmann 2005.Google Scholar
  2. 7.
    Handy, J.; The Cache Memory book; Academic Press; San Diego; CA 1998.Google Scholar
  3. 15.
  4. 23.
    Furber, S. et al. ARM3—32b RISC processor with 4kbyte on-chip cache, In G. Musgrave and U. Lauther, editors, Proc. IFIP TC 10/WG 10.5 Int. Conf. on VLSI, 1989, pp. 35-44.Google Scholar
  5. 25.
    Clark, L.T. et al. An Embedded 32-b Microprocessor Core for Low-Power and High-Performance Applications, IEEE J. Solid-State Circuits, volume 36, November 2001, pp. 1599-1608.CrossRefGoogle Scholar
  6. 26.
    Zhang, M. and Asanovic, K. Highly Associative Caches for Low-Power Processors, Kool Chips Workshop, 33rd International Symposium on Microarchitecture, December 2000.Google Scholar
  7. 50.
    Pagiamtzis, K.; Sheikholeslami, K. Content-Addressable Memory (CAM) Circuits and Architecture, IEEE J. Solid-State Circuits, volume 41, March 2006; pp. 712–727.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  • Baker Mohammad
    • 1
  1. 1.Khalifa University of Science, Technology and ResearchAbu DhabiUnited Arab Emirates

Personalised recommendations