Introduction

Abstract

Embedded memories are becoming an increasingly important part of processor and system-on-chip (SOC) because of their positive impact on performance. However, embedded memories can negatively impact area, power, timing, yield, and design time. The ever-increasing gap between processor frequencies and DRAM access times, popularly referred to as memory wall, has indicated that processors use more and more on-die memory, hence the name “Embedded memory” [1, 2]. In addition, the new paradigm of multi-core systems and multi-functional units on the same die driven by the need for power efficiency, multi-functioning and large data size for high performance also contributes to the increase of embedded memory size [3]. As a result, in many chips the memory arrays make-up more than 80 % of the device and occupy about half of the chip’s area [4]. Figure 1.1 shows an example of the embedded memory size trend of the Intel mobile processor [5].