Abstract
The idea of using an electric field to modulate the conductivity of a semiconductor was first proposed and patented by Lilienfeld in 1925 (Fig. 4.1). This type of field effect phenomenon is used today in various types of field effect transistors (FETs). The first demonstration of a working FET device occurred in 1948 with practical devices appearing around 1953.
“I looked at what we were doing in integrated circuits at that time (1965), and we made a few circuits and gotten up to 30 components on the most complex chips…working on 60…and in fact from the days of the original planar transistor, which was 1959, we had about doubled every year the amount of components we could put on a chip.”
G. E. Moore
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Notes
- 1.
W. Shockley, G. L. Pearson, Phys. Rev. 74, 232 (1948); G. C. Dacey, I. M. Ross, Proc. IRE 41, 970 (1953).
- 2.
D. Kahng, M. M. Atalla, IRE-AIEE Solid-State Device Res. Conf., Pittsburgh, 1960.
- 3.
Although the silicon dioxide layer is amorphous, it can be accurately modeled as a large band gap semiconductor.
- 4.
See Appendix A, Eq. (A.29).
- 5.
C. G. B. Garrett, W. H. Brattain, Phys. Rev. 99, 376 (1955).
- 6.
Recall, this condition arises from the conditions set by Maxwell’s equations on the displacement field (D x = ε 0 ε r E x ) normal to an interface, which in the absence of oxide surface charge must be continuous.
- 7.
- 8.
Note that in this case the gate voltage will be negative in order to induce a positive layer of mobile charge in the n-type substrate.
- 9.
Recall that capacitors in series sum like resistors in parallel.
- 10.
W. S. Boyle, G. E. Smith, Bell Syst. Tech. J. 49, 587 (1970).
- 11.
When in the ON state the channel is essentially a resistor.
- 12.
This is a one-dimensional version of the standard equation for current density J = qnv.
- 13.
The channel carrier mobility is reduced from bulk carrier mobility due to increased scattering at the oxide interface (see Appendix B).
- 14.
Sometimes also referred to simply as back-biasing.
- 15.
This is similar to the body-bias effect but with a changing (instead of constant) bias along the channel.
- 16.
Equation (4.37) tells us that the subthreshold current of a MOSFET can at most vary by one decade per 60 mV gate bias (often referred to as the subthreshold slope) at room temperature.
- 17.
As in previous chapters, we do not include non-idealities and other refinements when discussing the MOSFET small-signal parameters, but these can be included in a straightforward manner if necessary.
- 18.
In other words, the cut-off frequency is inversely proportional to the transit time.
- 19.
General binary logic functions such as NAND and NOR gates, etc., can also be implemented in a straightforward manner using CMOS circuits. (F. M. Wanlass, C. T. Sah, IEEE Int. Solid-State Circuits Conf., Philadelphia, PA, Feb. 1963.)
- 20.
The period for doubling has historically varied from about 1 to 3 years depending on the state of IC technology.
- 21.
The increased doping level is necessary to scale down the depletion width at the drain–substrate junction.
- 22.
In other words the MOS capacitor is partially charged by the depletion widths of the source and drain regions as they become comparable to the channel length and thus less charge needs to be induced by the gate voltage to reach inversion.
- 23.
See Appendix A, Sect. A.2 for further details.
- 24.
See Appendix B for inversion layer mobility data as a function of transverse electric field.
- 25.
In several technology “nodes” etching is used to reduce certain device dimensions below the nominal or “printed” minimum feature size.
- 26.
See Appendix A, Sect. A.3.
- 27.
A metal gate reduces resistance and maximizes the capacitive coupling of the gate to the channel.
- 28.
This implies that a channel with a large aspect ratio (tall and thin) would in principle provide opportunities for future scaling similar to the nonplanar capacitors used for DRAM.
- 29.
We have focused predominantly on device-related challenges associated with scaling. However, there is a range of other important issues that must be considered such as interconnects, fabrication, process integration, etc. [5].
- 30.
This problem may be somewhat difficult and/or lengthy.
References
Sze, S.M., Ng, K.K.: Physics of Semiconductor Devices, 3rd edn. Wiley Interscience, Hoboken (2007)
Muller, R.S., Kamins, T.I.: Device Electronics for Integrated Circuits, 3rd edn. Wiley, New York (2003)
Ng, K.K.: Complete Guide to Semiconductor Devices, 2nd edn. Wiley Interscience, New York (2002)
Streetman, B., Banerjee, S. Solid State Electronic Devices, 5th edn. Prentice-Hall (1999)
International Technology Roadmap for Semiconductors, ITRS, 2011–12; www.itrs.net
Pierret, R.F. Field Effect Devices, 2nd edn. Prentice-Hall (1990)
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Problems
Problems
-
1.
MOS band edge diagrams. Sketch the thermal equilibrium band edge diagram for a MOS system made with a gate material whose work function is greater than that of an n-type semiconductor substrate. (Assume zero oxide charge.)
-
2.
MOSFET design Footnote 29. A MOS system has a nickel gate (work function 5 eV) and 0.2 Ω-cm p-type silicon substrate. Assume there is an oxide surface charge density (Q f/q) = 3 × 1010cm− 2. (1) If the oxide thickness is 5 nm, determine V T (assume there is no additional substrate bias). (2) Design the channel dimensions so that the resulting MOSFET outputs a current of 1 mA when V G is 1 V above threshold and V D = 0.75 V. Assume long-channel theory applies with μ n = 320 cm2V− 1s− 1 and a bulk-charge factor of 1.4. (3) How small can your design be scaled before channel carrier velocity saturation at the source becomes a problem? (Hint: consider Eq. (4.25))
-
3.
Short-channel MOSFETs. Several of the short-channel effects caused by MOSFET scaling can be controlled by increasing the substrate doping level. What limits how heavily the substrate can be doped?
-
4.
Limits of MOSFET scaling. Consider direct source–drain tunneling as the factor that will ultimately limit silicon MOSFET scaling in the future to come up with a lower limit on channel length, L, when the end of scaling has been reached.
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Papadopoulos, C. (2014). Field Effect Transistors. In: Solid-State Electronic Devices. Undergraduate Lecture Notes in Physics. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-8836-1_4
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