Abstract
Graphics processing units (GPU) are increasing the speed and volume of computation possible in scientific computing applications. Much of the rapidly growing interest in GPUs today stems from the numerous reports of 10–100-fold speedups over traditional CPU-based systems. In contrast to traditional CPUs, which are designed to extract as much parallelism and performance as possible from sequential programs, GPUs are designed to efficiently execute explicitly parallel programs. In particular, GPUs excel in the case of programs that have inherent data-level parallelism, in which one applies the same operation to many data simultaneously. Applications in scientific computing frequently fit this model. This introductory chapter gives a brief history and overview of modern GPU systems, including the dominant programming model that has made the compute capabilities of GPUs accessible to the programming-literate scientific community. Its examples focus on GPU hardware and programming environment available from a particular vendor, NVIDIA, though the main principles apply to other systems.
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Notes
- 1.
It also explains why advocates of GPU design refer to GPUs as being especially suited to throughput-oriented execution, rather than latency-oriented execution as in CPUs.
- 2.
For instance, if a GPU kernel operates on a 2-D image, it is very likely most “natural” to assign one thread to perform a computation on each pixel; in this case, a 2-D logical organization of threads is likely to be a sensible way of mapping threads to work.
References
T. Blank. The maspar mp-1 architecture. In Compcon Spring ’90. Intellectual Leverage. Digest of Papers. Thirty-Fifth IEEE Computer Society International Conference., pages 20–24, 1990.
W. J. Bouknight, S.A. Denenberg, D.E. McIntyre, J. M. Randall, A.H. Sameh, and D.L. Slotnick. The illiac iv system. Proceedings of the IEEE, 60(4):369–388, 1972.
Ian Buck, Tim Foley, Daniel Horn, Jeremy Sugerman, Kayvon Fatahalian, Mike Houston, and Pat Hanrahan. Brook for gpus: stream computing on graphics hardware. ACM Trans. Graph., 23(3):777–786, August 2004.
W. Daniel Hillis. New computer architectures and their relationship to physics or why computer science is no good. International Journal of Theoretical Physics, 21(3–4):255–262, 1982.
M. Flynn. Some computer organizations and their effectiveness. Computers, IEEE Transactions on, C-21(9):948–960, 1972.
Michael D. McCool, Zheng Qin, and Tiberiu S. Popa. Shader metaprogramming. In Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware, HWWS ’02, pages 57–68, Aire-la-Ville, Switzerland, Switzerland, 2002. Eurographics Association.
NVIDIA. NVIDIA’s Next Generation CUDA Compute Architecture: Kepler GK110 Whitepaper. NVIDIA, Santa Clara, CA, USA.
NVIDIA. CUDA Toolkit Documentation. NVIDIA, Santa Clara, CA, USA, May 2013.
S. F. Reddaway. Dap–a distributed array processor. In Proceedings of the 1st annual symposium on Computer architecture, ISCA ’73, pages 61–65, New York, NY, USA, 1973. ACM.
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Vuduc, R., Choi, J. (2013). A Brief History and Introduction to GPGPU. In: Shi, X., Kindratenko, V., Yang, C. (eds) Modern Accelerator Technologies for Geographic Information Science. Springer, Boston, MA. https://doi.org/10.1007/978-1-4614-8745-6_2
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