Abstract
Discussed in this chapter is the electrostatic discharge (ESD) as the pervasive threat from fabrication, packaging to assembly operation of IC. The ESD robustness of the gate-all-around Silicon nanowire FETs and poly-Si nanowire thin-film FETs is characterized and compared with other types of FETs including bulk/SOI FinFETs and MOSFETs. The ESD performance is specified in terms of the figures of merit such as the failure current, trigger voltage, on-state resistance, leakage current, and failure current density, etc. By using these figures of merits, the ESD performance of nanowire FETs is characterized as a function of gate length, channel shape and material, operation modes (bipolar or diode), process variation, and layout topologies. Moreover, the failure mechanism of nanowire FETs subject to ESD stresses is investigated by means of electrical characterization, optical microscopic observation, and failure analysis. Finally, the optimal nanowire structure and design window are proposed in the light of the ESD performance evaluations presented.
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- ESD:
-
Electrostatic discharge
- IC:
-
Integrated circuits
- SOI:
-
Silicon-on-insulator
- HBM:
-
Human body model
- TLP:
-
Transmission line pulsing
- NWTFT:
-
Nanowire thin-film transistor
- NW:
-
Nanowire
- GAA NWFET:
-
Gate-all-around silicon nanowire field-effect transistor
- FOM:
-
Figure of merit
- SCS:
-
Semiconductor characterization system
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Liu, W., Liou, J.J. (2014). Characterization of Nanowire Devices Under Electrostatic Discharge Stress Conditions. In: Kim, D., Jeong, YH. (eds) Nanowire Field Effect Transistors: Principles and Applications. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-8124-9_6
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