Hardware Design of Individual Components
The previous chapters described the basic principles for the application channel coding. Before proceeding to advanced channel coding techniques and its possible hardware realization we will introduce in this chapter the basic steps for a hardware design. An entire receiver is large system and comprises many different functionalities. Combining all of them on a single die yields a so called System-on-a-Chip (SoC). The SoC design requires the knowledge from system specification down to hardware partitioning and refinement. However, every SoC is partitioned in smaller functional blocks which can then be developed individually on component level. This is especially true for the channel decoder which is just one single component in a larger system. The same hold for e.g. demodulator, source encoder or decoder and so on. The advantage of designing components individually is that typically the functionality is restricted and can be well described. In this chapter we first revise (Sect. 4.1) the design flow for a single component and show the different design constraints which are posed either by the communications domain or the hardware domain. Note, that the design flow shown here is no general hardware design flow. It is restricted to communications specific constraints with respect to the introduced base band processing components. Memories are an extremely important part for the entire SoC and for each individual component as well.
- 1.Mller, S., Schreger, M., Kabutz, M., Alles, M., Kienle, F., Wehn, N.: A novel LDPC decoder for DVB-S2 IP. In: Proc. DATE ’09. Design, Automation. Test in Europe Conference. Exhibition, pp. 1308–1313 (2009)Google Scholar
- 2.Sun, J., Takeshita, O.Y.: Interleavers for turbo codes using permutation polynomials over integer rings. IEEE Trans. Inf. Theory 51(1), 101–119 (2005). doi: 10.1109/TIT.2004.839478
- 3.Third Generation Partnership Project: 3GPP TS 36.212 V8.5.0; 3rd Generation Partnership Project; Technical Specification Group Radio Access Network; Evolved Universal Terrestrial Radio Access (E-UTRA); Multiplexing and channel coding (Release 8) (2008).www.3gpp.org
- 4.Nimbalker, A., Blankenship, Y., Classon, B., Blankenship, T.K.: ARP and QPP interleavers for LTE Turbo coding. In: Proceedings of the IEEE Wireless Communications and Networking Conference WCNC 2008, pp. 1032–1037 (2008). doi: 10.1109/WCNC.2008.187
- 5.Third Generation Partnership Project: 3GPP TS 25.212 V1.0.0; 3rd Generation Partnership Project (3GPP);Technical Specification Group (TSG) Radio Access Network (RAN); Working Group 1 (WG1); Multiplexing and channel coding (FDD) (1999). www.3gpp.org
- 6.European Telecommunications Standards Institude (ETSI): Digital Video Broadcasting (DVB) Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications; TM 2860r1 DVBS2-74r8. www.dvb.org