Advertisement

Application Analysis

  • Somnath Paul
  • Swarup Bhunia
Chapter

Abstract

This chapter describes the frontend of the application mapping flow for the MBC framework. The frontend of the flow accepts an application description in the format of a CDFG. The key step involved in the frontend is partitioning of input application into subtasks (decomposition) to facilitate mapping into the MLB functional units. The other important task is to cluster multiple small tasks into large macro functions which can be suitably mapped to a single functional unit (fusion). While decomposition ensures all input applications can be mapped to the MBC framework, the later step improves performance and energy-efficiency of the framework. Each of these steps involve one or more heuristics which are described in this chapter along with illustrations. The output from the frontend of the tool is a transformed CDFG description of the input application which is then picked up the backend of the software flow for scheduling and resource allocation.

References

  1. 1.
    [Online], “Graphviz - graph visualization software”. www.graphviz.org
  2. 2.
    F.D. Dinechin, A. Tisserand, “Multipartite table methods”. IEEE Trans. Comput. 54(3), 319–330 (2005)CrossRefGoogle Scholar
  3. 3.
    “Implementing Barrel Shifters Using Multipliers”. http://www.xilinx.com/support/documentation/application_notes/xapp195.pdf
  4. 4.
    E. Chung, J. Hoe, K. Mai, “CoRAM: An In-Fabric Memory Abstraction for FPGA-based Computing”, in Intl. Symposium on Field Programmable Gate Arrays, 2011Google Scholar
  5. 5.
    G. Karypis, “Multilevel hypergraph partitioning: applications in vlsi domain”. IEEE Trans. VLSI 7(1), 69–79 (1999)CrossRefGoogle Scholar
  6. 6.
    J. Cong, Y. Ding, “On Area/Depth Trade-Off in Lut-Based FPGA Technology Mapping”, in Design Automation Conference, 1993Google Scholar

Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  • Somnath Paul
    • 1
  • Swarup Bhunia
    • 2
  1. 1.Intel LabsHillsboroUSA
  2. 2.Department of EECSCase Western Reserve UniversityClevelandUSA

Personalised recommendations