Improvement in Energy-Efficiency with Off-Chip MAHA
This chapter first arrives at an optimal architecture for an off-chip MAHA framework based on SLC NAND Flash technology. The viability of mapping diverse applications to this framework is studied and the energy-efficiency of the mapped applications is compared against a baseline model, i.e. a software based execution with no acceleration. Next the efficiency of this off-chip accelerator with commercial FPGA and GPU based acceleration. Finally a details of an emulation setup which validates the functionality of the MAHA framework is presented. Both simulation and emulation results presented in this chapter confirm that an off-chip in-memory accelerator can reap considerable gains in energy-efficiency for data-intensive tasks.
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