Improvement in Energy-Efficiency with Off-Chip MAHA

  • Somnath Paul
  • Swarup Bhunia
Chapter

Abstract

This chapter first arrives at an optimal architecture for an off-chip MAHA framework based on SLC NAND Flash technology. The viability of mapping diverse applications to this framework is studied and the energy-efficiency of the mapped applications is compared against a baseline model, i.e. a software based execution with no acceleration. Next the efficiency of this off-chip accelerator with commercial FPGA and GPU based acceleration. Finally a details of an emulation setup which validates the functionality of the MAHA framework is presented. Both simulation and emulation results presented in this chapter confirm that an off-chip in-memory accelerator can reap considerable gains in energy-efficiency for data-intensive tasks.

References

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    V. Mohan, S. Gurumurthi, M.R. Stan, “FlashPower: A Detailed Power Model for NAND Flash Memory”, in DATE, 2010Google Scholar
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    [Online]. “Micron 1Gb NAND Flash Data Sheet”. http://download.micron.com/pdf/datasheets/flash/nand/1gb_nand_m48a.pdf
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Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  • Somnath Paul
    • 1
  • Swarup Bhunia
    • 2
  1. 1.Intel LabsHillsboroUSA
  2. 2.Department of EECSCase Western Reserve UniversityClevelandUSA

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