Off-Chip MAHA Using NAND Flash Technology

  • Somnath Paul
  • Swarup Bhunia


In this chapter, details of the hardware architecture for an off-chip MAHA framework based on CMOS-compatible Single Level Cell (SLC) NAND Flash memory array (Park et al. A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure, Intl. Solid-State Circuits Conference, 2008) are presented. CMOS-compatibility allows the integration of MLB controller (including registers, datapath and PI) realized using CMOS logic with the Flash process. Flash memory has seen an astounding increase in integration density over the last few years (Technologies for Data-Intensive Computing,, making it attractive storage system for data-intensive computing (Technologies for Data-Intensive Computing,; Kgil et al. Improving NAND Flash Based Disk Caches, Intl. Symp. on Computer Architecture, 2008). Although Multi-Level Cell (MLC) Flash has gained more popularity due to its high-integration density and low cost per bit, the consideration for SLC Flash is mainly driven by the availability of opensource area, power and delay models for the same (Mohan et al. FlashPower: A detailed power model for NAND flash memory, DATE, 2010). The proposed architecture, however, applies to MLC Flash memory as well.


Data Block Flash Memory Phase Change Memory NAND Flash Flash Translation Layer 
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Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  • Somnath Paul
    • 1
  • Swarup Bhunia
    • 2
  1. 1.Intel LabsHillsboroUSA
  2. 2.Department of EECSCase Western Reserve UniversityClevelandUSA

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