Background and Motivation

  • Somnath Paul
  • Swarup Bhunia
Chapter

Abstract

This chapter describes the Von-Neumann bottleneck and its effect in limiting the energy-efficiency of traditional compute hardware for processing data-intensive applications. For these applications, traditional approach of bringing data from off-chip memory to on-chip compute engines has been demonstrated to be ineffective in terms of energy-efficiency. In the era of big data, on-chip computing is restricted by both off-chip bandwidth and access energy. In such a scenario, an off-chip compute framework realized by instrumenting non-volatile memory can prove to be an effective solution in mitigating the Von-Neumann bottleneck. This chapter also discusses the nature of such an off-chip compute hardware and the applications which can benefit from it.

References

  1. 1.
    J. Backus, “Can programming style be liberated from the von-neumann style? A functional style and its algebra of programs”. ACM Comm. 21(8), 613–641 (1978)MathSciNetCrossRefMATHGoogle Scholar
  2. 2.
    E.S. Chung, P.A. Milder, J.C. Hoe, K. Mai, “Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs? in Intl. Symp. on Microarchitecture, 2010Google Scholar
  3. 3.
    P. Kogge et al., “ExaScale Computing Study: Technology Challenges in Achieving Exascale Systems”. http://www.cse.nd.edu/Reports/2008/TR-2008-13.pdf
  4. 4.
    V.W. Lee et al., “Debunking the 100X GPU vs. CPU Myth: An Evaluation of Throughput Computing on CPU and GPU”, in Intl. Symp. on Computer Architecture, 2010Google Scholar
  5. 5.
    R. Murphy, A. Rodrigues, P. Kogge, K. Underwood, “The Implications of Working Set Analysis on Supercomputing Memory Hierarchy Design”, in Intl. Conf. on Supercomputing, 2005.Google Scholar
  6. 6.
    “International Technology Roadmap for Semiconductors” http://www.itrs.net/links/2009ITRS/Home2009.htm.
  7. 7.
    E.S. Chung, P.A. Milder, J.C. Hoe, K. Mai, “Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?”, in Intl. Symp. on Microarchitecture, 2010Google Scholar
  8. 8.
    A. Sodani, “Race to Exascale: Opportunities and Challenges”. http://www.microarch.org/micro44/files/program.htm
  9. 9.
    P.M. Kogge. “From Petaflops to Exaflops”, in Intl. Supercomputing Conference, 2008Google Scholar
  10. 10.
    “Simplescalar Toolset v3.0” http://www.simplescalar.com/

Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  • Somnath Paul
    • 1
  • Swarup Bhunia
    • 2
  1. 1.Intel LabsHillsboroUSA
  2. 2.Department of EECSCase Western Reserve UniversityClevelandUSA

Personalised recommendations