Application Mapping to MBC Hardware
This chapter describes the key steps in mapping the CDFG output after partitioning and fusion to the MBC hardware. A description for the MBC hardware serves as an input to the backend of the software flow. The number of MLB resources and their organization dictate the decisions made by the flow during scheduling, resource allocation, placement and routing. The output from the backend is a bitfile which can be directly loaded into the MBC hardware. The flow is also capable of estimating the power and performance of the input application, provided the power and performance for the individual MLBs and the programable interconnect is provided as an input to the flow.
- 1.K.K. Parhi, “VLSI Digital Signal Processing Systems: Design and Implementation” John Wiley & Sons (1999)Google Scholar
- 3.[Online], “Improving FPGA Performance and Area Using an Adaptive Logic Module”. www.altera.com/literature/cp/cp-01004.pdf
- 4.[Online], “VPR and T-VPack 5.0.2 Full CAD Flow for Heterogeneous FPGAs”. http://www.eecg.utoronto.ca/vpr/
- 5.[Online], “iFAR – intelligent FPGA Architecture Repository”. http://www.eecg.utoronto.ca/vpr/architectures/
- 6.[Online], “CACTI 5.1”. http://www.hpl.hp.com/techreports/2008/HPL-2008-20.html