Abstract
Modern integrated circuit designers must deal with complex design and simulation problems while coping with large device to device parametric variations and often imperfect information. This chapter presents surrogate model-based methods to generate circuit performance models for design, device models, and high-speed input-output (IO) buffer macromodels. Circuit performance models are built with design parameters and parametric variations, and they can be used for fast and systematic design space exploration and yield analysis. Surrogate models of the main device characteristics are generated in order to assess the effects of variability in analog circuits. The variation-aware IO buffer macromodel integrates surrogate modeling and a physically based model structure. The new IO macromodel provides both good accuracy and scalability for signal integrity analysis.
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Acknowledgements
The chapter has the distribution statement “A” (Approved for Public Release, Distribution Unlimited). The views expressed are those of the authors and do not reflect the official policy or position of the Department of Defense or the U.S. Government. This work was supported by the Self-HEALing mixed-signal Integrated Circuits (HEALICs) program of the Defense Advanced Research Projects Agency (DARPA) and the prime contractor Raytheon Company (Contract number: FA8650-09-C-7925).
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Zhu, T., Yelten, M.B., Steer, M.B., Franzon, P.D. (2013). Model-Based Variation-Aware Integrated Circuit Design. In: Koziel, S., Leifsson, L. (eds) Surrogate-Based Modeling and Optimization. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-7551-4_8
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DOI: https://doi.org/10.1007/978-1-4614-7551-4_8
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