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Handbook of Signal Processing Systems pp 945–974Cite as

DSP Instruction Set Simulation

Abstract

An instruction set simulator is an important tool for system architects and for software developers. However, when implementing a simulator, there are many choices which can be made and that have an effect on the speed and the accuracy of the simulation. They are especially relevant to DSP simulation. This chapter explains the different strategies for implementing a simulator.

Keywords

  • Virtual Machine
  • Basic Block
  • Design Space Exploration
  • Java Virtual Machine
  • Machine Code

These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Notes

  1. 1.

    http://unisim.org/site/

  2. 2.

    http://www.ics.uci.edu/~express/

  3. 3.

    http://archc.sourceforge.net/

  4. 4.

    http://www.llvm.org/

References

  1. Almer, O., Böhm, I., von Koch, T.J.K.E., Franke, B., Kyle, S.C., Seeker, V., Thompson, C., Topham, N.P.: Scalable multi-core simulation using parallel dynamic binary translation. In: International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, ICSAMOS ’11, pp. 190–199. IEEE (2011)

    Google Scholar 

  2. August, D., Chang, J., Girbal, S., Gracia-Perez, D., Mouchard, G., Penry, D.A., Temam, O., Vachharajani, N.: UNISIM: An open simulation environment and library for complex architecture design and collaborative development. IEEE Computer Architecture Letters 6(2), 45–48 (2007)

    CrossRef  Google Scholar 

  3. Austin, T., Larson, E., Ernst, D.: SimpleScalar: An infrastructure for computer system modeling. Computer 35(2), 59–67 (2002)

    CrossRef  Google Scholar 

  4. Azevedo, R., Rigo, S., Bartholomeu, M., Araujo, G., Araujo, C., Barros, E.: The ArchC architecture description language and tools. Int. J. Parallel Program. 33(5), 453–484 (2005). DOI http://dx.doi.org/10.1007/s10766-005-7301-0

    Google Scholar 

  5. Bartholomeu, M., Azevedo, R., Rigo, S., Araujo, G.: Optimizations for compiled simulation using instruction type information. In: Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2004), pp. 74–81 (2004). DOI http://doi.ieeecomputersociety.org/10.1109/CAHPC.2004.28

  6. Bell, J.R.: Threaded code. Commun. ACM 16(6), 370–372 (1973). DOI http://doi.acm.org/10.1145/362248.362270

  7. Bermudo, N., Horspool, N., Krall, A.: Control flow graph reconstruction for reverse compilation of assembly language programs with delayed instructions. In: SCAM’05: Proceedings of the Fifth International Workshop on Source Code Analysis and Manipulation, pp. 107–116 (2005)

    Google Scholar 

  8. Böhm, I., von Koch, T.J.K.E., Kyle, S.C., Franke, B., Topham, N.: Generalized just-in-time trace compilation using a parallel task farm in a dynamic binary translator. ACM SIGPLAN Notices 46(6), 74–85 (2011). DOI http://dx.doi.org/10.1145/1993316.1993508

  9. Brandner, F.: Precise simulation of interrupts using a rollback mechanism. In: SCOPES ’09: Proceedings of the 12th International Workshop on Software and Compilers for Embedded Systems, pp. 71–80 (2009)

    Google Scholar 

  10. Brandner, F., Fellnhofer, A., Krall, A., Riegler, D.: Fast and accurate simulation using the LLVM compiler framework. In: RAPIDO ’09: 1st Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (2009)

    Google Scholar 

  11. Burtscher, M., Ganusov, I.: Automatic synthesis of high-speed processor simulators. In: MICRO 37: Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, pp. 55–66 (2004). DOI http://dx.doi.org/10.1109/MICRO.2004.7

  12. Chiou, D., Sanjeliwala, H., Sunwoo, D., Xu, J.Z., Patil, N.: FPGA-based fast, cycle-accurate, full-system simulators. In: WARFP’06: Proceedings of the second Workshop on Architecture Research using FPGA Platforms (2006)

    Google Scholar 

  13. Chiou, D., Sunwoo, D., Kim, J., Patil, N., Reinhart, W.H., Johnson, D.E., Xu, Z.: The FAST methodology for high-speed SoC/computer simulation. In: ICCAD ’07: Proceedings of the 2007 IEEE/ACM International Conference on Computer-Aided Design, pp. 295–302 (2007)

    Google Scholar 

  14. Chiou, D., Sunwoo, D., Kim, J., Patil, N.A., Reinhart, W., Johnson, D.E., Keefe, J., Angepat, H.: FPGA-accelerated simulation technologies (FAST): Fast, full-system, cycle-accurate simulators. In: MICRO ’07: Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 249–261 (2007). DOI http://dx.doi.org/10.1109/MICRO.2007.16

  15. Chung, E.S., Hoe, J.C., Falsafi, B.: ProtoFlex: Co-simulation for component-wise FPGA emulator development. In: WARFP ’06: In Proceedings of the 2nd Workshop on Architecture Research using FPGA Platforms (2006)

    Google Scholar 

  16. Chung, E.S., Nurvitadhi, E., Hoe, J.C., Falsafi, B., Mai, K.: A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs. In: FPGA ’08: Proceedings of the 16th International ACM/SIGDA Symposium on Field Programmable Gate Arrays, pp. 77–86 (2008). DOI http://doi.acm.org/10.1145/1344671.1344684

  17. Chung, E.S., Papamichael, M.K., Nurvitadhi, E., Hoe, J.C., Mai, K., Falsafi, B.: ProtoFlex: Towards scalable, full-system multiprocessor simulations using FPGAs. ACM Transactions on Reconfigurable Technology and Systems (TRETS 2(2), 1–32 (2009)

    Google Scholar 

  18. Cmelik, B., Keppel, D.: Shade: A fast instruction-set simulator for execution profiling. In: SIGMETRICS ’94: Proceedings of the 1994 ACM SIGMETRICS Conference on Measurement and Modeling of Computer Systems, pp. 128–137 (1994)

    Google Scholar 

  19. Cofer, R.C., Harding, B.: Rapid System Prototyping with FPGAs: Accelerating the Design Process. Newnes (2005)

    Google Scholar 

  20. Dehnert, J.C., Grant, B.K., Banning, J.P., Johnson, R., Kistler, T., Klaiber, A., Mattson, J.: The Transmeta Code MorphingTM software: Using speculation, recovery, and adaptive retranslation to address real-life challenges. In: CGO ’03: Proceedings of the International Symposium on Code Generation and Optimization, pp. 15–24 (2003)

    Google Scholar 

  21. Ebcioğlu, K., Altman, E., Gschwind, M., Sathaye, S.: Dynamic binary translation and optimization. IEEE Transactions on Computers 50(6), 529–548 (2001)

    CrossRef  Google Scholar 

  22. Ebcioğlu, K., Altman, E.R.: DAISY: Dynamic compilation for 100% architectural compatibility. In: ISCA ’97: Proceedings of the 24th International Symposium on Computer Architecture, pp. 26–37 (1997)

    Google Scholar 

  23. Ebcioğlu, K., Altman, E.R., Gschwind, M., Sathaye, S.: Optimizations and oracle parallelism with dynamic translation. In: MICRO 32: Proceedings of the 32nd annual ACM/IEEE International Symposium on Microarchitecture, pp. 284–295 (1999)

    Google Scholar 

  24. Emer, J., Ahuja, P., Borch, E., Klauser, A., Luk, C.K., Manne, S., Mukherjee, S.S., Patil, H., Wallace, S., Binkert, N., Espasa, R., Juan, T.: Asim: A performance model framework. Computer 35(2), 68–76 (2002). DOI http://dx.doi.org/10.1109/2.982918

    Google Scholar 

  25. Errico, J.D., Qin, W.: Constructing portable compiled instruction-set simulators - an ADL-driven approach. In: DATE ’06: Proceedings of the Conference on Design, Automation and Test in Europe, pp. 112–117 (2006)

    Google Scholar 

  26. Farfeleder, S., Krall, A., Horspool, N.: Ultra fast cycle-accurate compiled emulation of inorder pipelined architectures. EUROMICRO Journal of Systems Architecture 53(8), 501–510 (2007)

    CrossRef  Google Scholar 

  27. Fauth, A., Praet, J.V., Freericks, M.: Describing instruction set processors using nML. In: EDTC ’95: Proceedings of the 1995 European Conference on Design and Test, pp. 503–507 (1995)

    Google Scholar 

  28. Fytraki, S., Pnevmatikatos, D.: ReSim, a trace-driven, reconfigurable ILP processor simulator. In: DATE ’09: Proceedings of Design, Automation and Test in Europe 2009 (2009)

    Google Scholar 

  29. Gao, L., Kraemer, S., Leupers, R., Ascheid, G., Meyr, H.: A fast and generic hybrid simulation approach using C virtual machine. In: CASES ’07: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, pp. 3–12 (2007)

    Google Scholar 

  30. Goossens, G., Lanneer, D., Geurts, W., Praet, J.V.: Design of ASIPs in multi-processor SoCs using the Chess/Checkers retargetable tool suite. In: International Symposium on System-on-Chip, pp. 1–4 (2006). DOI 10.1109/ISSOC.2006.321968

  31. Gschwind, M., Altman, E.: Optimization and precise exceptions in dynamic compilation. ACM SIGARCH Computer Architecture News 29(1), 66–74 (2001)

    CrossRef  Google Scholar 

  32. Gschwind, M., Altman, E.R., Sathaye, S., Ledak, P., Appenzeller, D.: Dynamic and transparent binary translation. Computer 33(3), 54–59 (2000). DOI http://dx.doi.org/10.1109/2.825696

    Google Scholar 

  33. Halambi, A., Grun, P., Ganesh, V., Khare, A., Dutt, N., Nicolau, A.: EXPRESSION: A language for architecture exploration through compiler/simulator retargetability. In: DATE ’99: Proceedings of the Conference on Design, Automation and Test in Europe, pp. 485–490 (1999). DOI http://doi.acm.org/10.1145/307418.307549

  34. Horspool, R.N., Marovac, N.: An approach to the problem of detranslation of computer programs. Comput. J. 23(3), 223–229 (1980)

    CrossRef  Google Scholar 

  35. Ienne, P., Leupers, R.: Customizable Embedded Processors: Design Technologies and Applications (Systems on Silicon). Morgan Kaufmann Publishers Inc., San Francisco, CA, USA (2006)

    Google Scholar 

  36. Jones, D., Topham, N.P.: High speed CPU simulation using LTU dynamic binary translation. In: HiPEAC’09: Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers, pp. 50–64 (2009)

    Google Scholar 

  37. Klint, P.: Interpretation techniques. Software: Practice and Experience 11(9), 963 – 973 (1981)

    CrossRef  Google Scholar 

  38. Krall, A., Farfeleder, S., Horspool, N.: Ultra fast cycle-accurate compiled emulation of inorder pipelined architectures. In: SAMOS ’05: Proceedings of the International Workshop on Systems, Architectures, Modeling, and Simulation, LNCS 3553, pp. 222–231 (2005)

    Google Scholar 

  39. Kudlugi, M., Hassoun, S., Selvidge, C., Pryor, D.: A transaction-based unified simulation/emulation architecture for functional verification. In: DAC ’01: Proceedings of the 38th Conference on Design Automation, pp. 623–628 (2001). DOI http://doi.acm.org/10.1145/378239.379036

  40. Lantz, R.E.: Fast functional simulation with parallel Embra. In: 4th Annual Workshop on Modeling, Benchmarking and Simulation, MOBS’08 (2008)

    Google Scholar 

  41. Larus, J.: Assemblers, linkers and the SPIM simulator. In: D.A. Patterson, J.L. Hennessy (eds.) Computer Organization and Design: The Hardware/software Interface. Morgan Kaufmann (2005)

    Google Scholar 

  42. Magnusson, P.S.: Efficient instruction cache simulation and execution profiling with a threaded-code interpreter. In: WSC ’97: Proceedings of the 29th Conference on Winter Simulation, pp. 1093–1100 (1997). DOI http://doi.acm.org/10.1145/268437.268745

  43. Magnusson, P.S., Christensson, M., Eskilson, J., Forsgren, D., Hållberg, G., Högberg, J., Larsson, F., Moestedt, A., Werner, B.: Simics: A full system simulation platform. Computer 35(2), 50–58 (2002)

    CrossRef  Google Scholar 

  44. May, C.: Mimic: a fast System/370 simulator. In: Symposium on Interpreters and Interpretive Techniques, pp. 1–13 (1987). DOI http://doi.acm.org/10.1145/29650.29651

  45. Mills, C., Ahalt, S.C., Fowler, J.: Compiled instruction set simulation. Software: Practice and Experience 21(8), 877–889 (1991)

    CrossRef  Google Scholar 

  46. Mishra, P., Dutt, N.: Processor Description Languages, Volume 1. Morgan Kaufmann Publishers Inc., San Francisco, CA, USA (2008)

    Google Scholar 

  47. Nakamura, Y., Hosokawa, K.: Fast FPGA-emulation-based simulation environment for custom processors. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E89-A(12), 3464–3470 (2006)

    CrossRef  Google Scholar 

  48. Nakamura, Y., Hosokawa, K., Kuroda, I., Yoshikawa, K., Yoshimura, T.: A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication. In: DAC ’04: Proceedings of the 41st annual Conference on Design Automation, pp. 299–304 (2004). DOI http://doi.acm.org/10.1145/996566.996655

  49. Nohl, A., Braun, G., Schliebusch, O., Leupers, R., Meyr, H., Hoffmann, A.: A universal technique for fast and flexible instruction-set architecture simulation. In: DAC ’02: Proceedings of the 39th Conference on Design Automation, pp. 22–27 (2002)

    Google Scholar 

  50. Pees, S., Hoffmann, A., Meyr, H.: Retargetable compiled simulation of embedded processors using a machine description language. ACM Transactions on Design Automation of Electronic Systems. 5(4), 815–834 (2000)

    CrossRef  Google Scholar 

  51. Pellauer, M., Vijayaraghavan, M., Adler, M., Arvind, Emer, J.: A-Ports: An efficient abstraction for cycle-accurate performance models on FPGAs. In: FPGA ’08: Proceedings of the 16th International ACM/SIGDA Symposium on Field Programmable Gate Arrays, pp. 87–96 (2008). DOI http://doi.acm.org/10.1145/1344671.1344685

  52. Pellauer, M., Vijayaraghavan, M., Adler, M., Arvind, Emer, J.: Quick performance models quickly: Closely-coupled partitioned simulation on FPGAs. In: ISPASS ’08: IEEE International Symposium on Performance Analysis of Systems and Software, pp. 1–10 (2008). DOI 10.1109/ISPASS.2008.4510733

  53. Proebsting, T.A.: Optimizing an ANSI C interpreter with superoperators. In: POPL ’95: Proceedings of the 22nd ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, pp. 322–332 (1995). DOI http://doi.acm.org/10.1145/199448.199526

  54. Qin, W., D’Errico, J., Zhu, X.: A multiprocessing approach to accelerate retargetable and portable dynamic-compiled instruction-set simulation. In: Proceedings of the 4th international conference on Hardware/software codesign and system synthesis, CODES+ISSS ’06, pp. 193–198. ACM, New York, NY, USA (2006). DOI http://doi.acm.org/10.1145/1176254.1176302. URL http://doi.acm.org/10.1145/1176254.1176302

  55. Raghav, S., Ruggiero, M., Atienza, D., Pinto, C., Marongiu, A., Benini, L.: Scalable instruction set simulator for thousand-core architectures running on gpgpus. In: International Conference on High Performance Computing and Simulation, HPCS ’10, pp. 459–466. IEEE (2010). DOI 10.1109/HPCS.2010.5547092

  56. Reshadi, M., Dutt, N.: Generic pipelined processor modeling and high performance cycle-accurate simulator generation. In: DATE ’05: Proceedings of the Conference on Design, Automation and Test in Europe, pp. 786–791 (2005). DOI http://dx.doi.org/10.1109/DATE.2005.166

  57. Reshadi, M., Dutt, N., Mishra, P.: A retargetable framework for instruction-set architecture simulation. ACM Transactions on Embedded Computing Systems (TECS) 5(2), 431–452 (2006)

    Google Scholar 

  58. Reshadi, M., Mishra, P., Dutt, N.: Instruction set compiled simulation: A technique for fast and flexible instruction set simulation. In: Proceedings of the 40th Conference on Design Automation, pp. 758–763 (2003). DOI http://doi.acm.org/10.1145/775832.776026

  59. Reshadi, M., Mishra, P., Dutt, N.: Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation. ACM Transactions on Embedded Computing Systems (TECS) 8(3), 1–27 (2009)

    Google Scholar 

  60. Roeven, H., Coninx, J., Ade, M.: CoolFlux DSP: The embedded ultra low power C-programmable DSP core. In: GSPx’04: International Signal Processing Conference, pp. 1–7 (2004)

    Google Scholar 

  61. Rosenblum, M., Herrod, S.A., Witchel, E., Gupta, A.: Complete computer system simulation: The SimOS approach. IEEE Parallel & Distributed Technology 3(4), 34–43 (1995)

    CrossRef  Google Scholar 

  62. Sathaye, S., Ledak, P., Leblanc, J., Kosonocky, S., Gschwind, M., Fritts, J., Bright, A., Altman, E., Agricola, C.: BOA: Targeting multi-gigahertz with binary translation. In: In Proceedings of the 1999 Workshop on Binary Translation, pp. 2–11 (1999)

    Google Scholar 

  63. Schnerr, J., Bringmann, O., Rosenstiel, W.: Cycle accurate binary translation for simulation acceleration in rapid prototyping of SoCs. In: DATE ’05: Proceedings of the Conference on Design, Automation and Test in Europe, pp. 792–797 (2005). DOI http://dx.doi.org/10.1109/DATE.2005.106

  64. Schnerr, J., Haug, G., Rosenstiel, W.: Instruction set emulation for rapid prototyping of SoCs. In: DATE ’03: Proceedings of the Conference on Design, Automation and Test in Europe, pp. 562–567 (2003)

    Google Scholar 

  65. Sites, R.L., Chernoff, A., Kirk, M.B., Marks, M.P., Robinson, S.G.: Binary translation. Communications of the ACM 36(2), 69–81 (1993). DOI http://doi.acm.org/10.1145/151220.151227

  66. Smith, J.E., Nair, R.: Virtual Machines. Morgan Kaufman (2005)

    Google Scholar 

  67. Suh, T., Lee, H.H.S., Lu, S.L., Shen, J.: Initial observations of hardware/software co-simulation using FPGA in architectural research. In: WARFP’06: In Proceedings of the 2nd Workshop on Architecture Research using FPGA Platforms (2006)

    Google Scholar 

  68. Open SystemC Initiative. http://www.systemc.org/home

  69. Vachharajani, M., Vachharajani, N., August, D.I.: The Liberty Structural Specification Language: A high-level modeling language for component reuse. In: PLDI ’04: Proceedings of the ACM SIGPLAN 2004 Conference on Programming Language Design and Implementation, pp. 195–206 (2004)

    Google Scholar 

  70. Vachharajani, M., Vachharajani, N., Penry, D.A., Blome, J.A., Malik, S., August, D.I.: The Liberty Simulation Environment: A deliberate approach to high-level system modeling. ACM Transactions on Computer Systems 24(3), 211–249 (2006)

    CrossRef  Google Scholar 

  71. Wang, K., Zhang, Y., Wang, H., Shen, X.: Parallelization of IBM Mambo system simulator in functional modes. SIGOPS Oper. Syst. Rev. 42, 71–76 (2008). DOI http://doi.acm.org/10.1145/1341312.1341325. URL http://doi.acm.org/10.1145/1341312.1341325

  72. Wang, Z., Liu, R., YufeiChen, Wu, X., Chen, H., Zhang, W., Zang, B.: COREMU: a scalable and portable parallel full-system emulator. In: Proceedings of the 16th ACM symposium on Principles and Practice of Parallel Programming, pp. 213–222. ACM (2011). URL http://doi.acm.org/10.1145/1941553.1941583

  73. Witchel, E., Rosenblum, M.: Embra: Fast and flexible machine simulation. In: SIGMETRICS ’96: Proceedings of the 1996 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, pp. 68–79 (1996)

    Google Scholar 

  74. Yi, J.J., Lilja, D.J.: Simulation of computer architectures: Simulators, benchmarks, methodologies, and recommendations. IEEE Transactions on Computers 55(3), 268–280 (2006)

    CrossRef  Google Scholar 

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Author information

Authors and Affiliations

  1. Department of Applied Mathematics and Computer Science, Technical University of Denmark, Kongens Lyngby, Denmark

    Florian Brandner

  2. Department of Computer Science, University of Victoria, Victoria, BC, Canada

    Nigel Horspool

  3. Institut für Computersprachen, Technische Universität Wien, Vienna, Austria

    Andreas Krall

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  1. Florian Brandner
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  2. Nigel Horspool
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Correspondence to Florian Brandner .

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Editors and Affiliations

  1. , Dept. of Electrical and, University of Maryland, A. V. Williams Bldg. 2311, College Park, 20742, Maryland, USA

    Shuvra S. Bhattacharyya

  2. Leiden Inst. Advanced Computer Science, Leiden Embedded Research Center, Leiden University, Niels Bohrweg 1, Leiden, 2333 CA, Netherlands

    Ed F. Deprettere

  3. Software for Systems on Silicon, RWTH Aachen University, Templergraben 55, Aachen, 52056, Germany

    Rainer Leupers

  4. , Department of Pervasive Computing, Tampere University of Technology, Korkeakoulunkatu 1, Tampere, 33720, Finland

    Jarmo Takala

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Brandner, F., Horspool, N., Krall, A. (2013). DSP Instruction Set Simulation. In: Bhattacharyya, S., Deprettere, E., Leupers, R., Takala, J. (eds) Handbook of Signal Processing Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-6859-2_29

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